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參數(shù)資料
| 型號(hào)： | PLB2224 |
| 英文描述： | 24+2G Switch On a Chip with Embedded Memory |
| 中文描述： | 24第二代開(kāi)關(guān)與嵌入式內(nèi)存芯片 |
| 文件頁(yè)數(shù)： | 29/219頁(yè) |
| 文件大?。?/td> | 2975K |
| 代理商： | PLB2224 |
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GREEN
PLB 2224
Functional Description
Data Sheet
29
2002-06-03
3.1
Introduction
Figure 10
shows the functional block diagram of PLB 2224. Each of the 24 Serial Media
Independent Interface ports consists of a configurable MAC core, which supports back
pressure, MII management, programmable backoff & full duplex. Each port has 256-byte
RX & 224 byte TX FIFOs & 802.3x flow control.
Two 10/100/1000 interfaces consists ofa configurable GMAC core. The Fast Ethernet
interface with the MAC’s are via SMII ports only. The 10/100/1000 Gigabit port can
interface to external transceivers via the Gigabit Media Independent Interface (GMII) or
Ten Bit Interface (TBI). The Gigabit interfaces include a Physical Coding Sublayer (PCS)
block, which can be used when interfacing to fiber via TBI. The PCS block can be
bypassed when the GMII is used with copper transceivers.
The Address Resolution Logic & Queue manager support both 802.1p & 802.1Q for
traffic class prioritization of multimedia or real time applications & also for increased
security, simplified moves/changes & fault localization. Support for Port based & TAG
based VLAN is provided. PLB 2224 can support up to 1022 Tag/port based VLAN,
making it ideal for emerging MDU/MTU market.
PLB 2224 supports Two levels of priority per output port. This allows for time sensitive
data to have access to the network with minimal latency. The Packet & Queue manager
implements a Hardware based Flow control. The Watermarks for the Flow control can
be programmed via external CPU. The onchip embedded DRAM is used entirely for
Packet buffering.
The Packet buffer is organized as buckets of 1536 bytes. The packet manager controls
the utilization & allocation of the packet buffer in a dynamic fashion.
The packet buffer is physically implemented with 2 banks of 256-bit wide DRAM, running
at 100 MHz, giving a raw memory bandwidth of up to 16 Gigabit per second.
The IEEE 802.1Q Port & VLAN based tagging is done via the Address Resolution Logic
& the TX blocks. They can handle up to 1024 VLANs for broadcast traffic isolation
purposes (including the membership corresponding to entries of "0" & "1023").
For Network management purposes RMON groups 1,2,3 & 9 are fully supported using
32-bit wide counters. Additional debugging features are offered by Port Mirroring
support. Port Based Traffic can be copied to any designate Port or CPU.
IP multicast is supported via Software for sending Data streams to multiple nodes. The
INTERNET GROUP MANAGEMENT PROTOCOL (IGMP) is supported to further
reduce the IP multicast streams, by forwarding packets to only those nodes which are
requesting them.
Spanning Tree software is supported for eliminating redundant links as well as loops in
the network. IP BOOTP & DHCP software is supported for automatic assignment of IP
addresses in intelligent system configuration
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