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參數(shù)資料
| 型號： | PLB2224 |
| 英文描述： | 24+2G Switch On a Chip with Embedded Memory |
| 中文描述： | 24第二代開關(guān)與嵌入式內(nèi)存芯片 |
| 文件頁數(shù)： | 33/219頁 |
| 文件大?。?/td> | 2975K |
| 代理商： | PLB2224 |
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GREEN
PLB 2224
Functional Description
Data Sheet
33
2002-06-03
MDIO addresses #4 and #5 Gigabit Ethernet Ports #0 and #1
MDIO addresses #8 through #31 <-> 10/100 Ethernet Ports #0 through #23
3.2.2
Receive Module (RX)
The RX Interfaces to the GMAC/MAC, handles all signals in both Full Duplex (FD) and
Half Duplex (HD) modes of operation. It also determines whether packet is SNAP
encapsulated/VLAN tagged. If VLAN tagged, VLAN ID and priority is communicated to
ARL. The RX block also forms Packet Header (PBH) information. PBH is written to the
eDRAM along with the packet data. Data is written to the eDRAM in 32-byte bursts. Each
1536-byte segment can be referenced using a Packet Numbers (pbnum), which are
obtained from Packet & Queue Manager (PQC). It Discards packets less than 64 byte in
length. It also consist of MIB counters to support RMON Ethernet statistics group.
Interfacing with ARL/eDRAM is implemented via synchronous handshaking.
It makes decision on dropping frames with errors (CRC error/FIFO overrun/Collision
Fragment etc.), PAUSE frames and non-tagged frames when so programmed. It also
supports port based mirroring. Support for up to 1022 VLANs /Multicast groups (802.1Q/
802.1D) is provided.
MAC Rx and Port Rx
The MAC Rx block implements the media access functionality for the 10/100 ports as
per the IEEE 802.3 standard. It strips the preamble of the incoming Ethernet packet,
deserializes the data, checks for legal packet length and correct CRC. Any packets
longer than the maximum allowed length of 1536 byte are truncated. If a CRC error is
found, the crc_err bit in the Packet Buffer Header (PBH) is set.
Several configuration bits control the behavior of the MAC Rx block. These configuration
options are described in the section Port Configuration, Status and Event Registers.
When a port is in full duplex mode with flow control enabled, the MAC Rx block
processes the PAUSE frames it receives and communicates the flow control status to
the MAC Tx block. The MAC Rx block also requests the MAC Tx block to send PAUSE
frames if necessary. A PAUSE frame received at MAC Rx is not forwarded to the
destination address unless
rx_pause_frame
bit Switch Configuration Register is set to 1.
The Port Rx block receives packet data from the MAC Rx and segments it into an 8-byte
chunk followed by a number of 32-byte chunks. The 8-byte chunk is stored in the SRAM
while the remaining packet data (i.e., all the 32-byte chunks including the very last chunk,
which could be 32-byte or less) is stored in the EDRAM. In addition, the Port Rx blocks
extracts the 6-byte SA and 6-byte DA from the packet and sends them to the ARL block
in the Switch Controller. The SA is looked up for learning and update. The DA is looked
up for determining the destination port(s) for the packet.
The Port Rx block creates a packet header (PBH) to record packet related information
such as the packet length, CRC status, source port id (src_pid) and the SDRAM number
in which the first 32-byte chunk of packet data is stored.
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