
QuadFALC
TM
PEF 22554 E
Pin Descriptions
Data Sheet
80
Rev. 1.2, 2006-01-26
B9
XPA1
O
–
General Purpose Output High (GPOH), port 1
PC(1:4).XPC(3:0) = 1010
B
The pin level is set fix to high level.
B11
XPB1
C9
XPC1
D9
XPD1
B9
XPA1
O
–
General Purpose Output Low (GPOL), port 1
PC(1:4).XPC(3:0) = 1011
B
The pin level is set fix to high level.
B11
XPB1
C9
XPC1
D9
XPD1
B9
XPA1
I
PU
Transmit Line Tristate, low active, port 1
XLT : PC(1:2).XPC(3:0) = 1110
B
A low level on this port sets the transmit lines XL1/2 or
XDOP/N into tristate mode. This pin function is logically ored
with register bit XPM2.XLT.
B11
XPB1
C9
XPC1
D9
XPD1
C7,
C8,
B5,
B7
XPA2
XPB2
XPC2
XPD2
I/O
PU/–
Transmit Multifunction Pins A to D, port 2
Depending on programming of bits PC(1:4).XPC(3:0) these
multifunction ports carry information to the system interface
or from the system to the QuadFALC
TM. After reset the ports
are configured to be inputs. With the selection of the
appropriate pin function, the corresponding input/output
configuration is achieved automatically. Depending on bit
SIC3.RESX latching/transmission of data is done with the
rising or falling edge of SCLKX. If not connected, an internal
pullup transistor ensures a high input level.
Each input function (SYPX, XMFS, XSIG,TCLK, XLT or XLT)
may only be selected once. SYPX and XMFS must not be
used in parallel.
Selectable pin functions as described for port 1.
L6,
N7,
N5,
L7
XPA3
XPB3
XPC3
XPD3
I/O
PU/–
Transmit Multifunction Pins A to D, port 3
Depending on programming of bits PC(1:4).XPC(3:0) these
multifunction ports carry information to the system interface
or from the system to the QuadFALC
TM. After reset the ports
are configured to be inputs. With the selection of the
appropriate pin function, the corresponding input/output
configuration is achieved automatically. Depending on bit
SIC3.RESX latching/transmission of data is done with the
rising or falling edge of SCLKX. If not connected, an internal
pullup transistor ensures a high input level.
Each input function (SYPX, XMFS, XSIG,TCLK, XLT or XLT)
may only be selected once. SYPX and XMFS must not be
used in parallel.
Selectable pin functions as described for port 1.
Table 2
I/O Signals for P/PG-LBGA-160-1 (cont’d)
Ball No. Name
Pin Type
Buffer
Type
Function