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Data Sheet
49
Rev. 1.2, 2006-01-26
QuadFALC
TM
PEF 22554 E
Pin Descriptions
4RPA1
O
–
General Purpose Output Low (GPOL), port 1
PC(1:4).RPC(3:0) = 1011
B.
The pin level is set fix to low level.
5RPB1
6RPC1
7RPD1
4RPA1
O
–
Loss of Signal Indication Output (LOS), port 1
PC(1:4).RPC(3:0) = 1100
B.
The output reflects the Loss of Signal status as readable in
FRS0.LOS.
5RPB1
6RPC1
7RPD1
4RPA1
I
PU
Receive TDM System Interface Tristate (RTDMT), port 1
PC(1:4).RPC(3:0) = 1101
B.
Controlling of tristate mode for RDO, RSIG,SCLKR and
RFM. The RTDMT value is logically exored with the register
bit SIC3.RRTRI.
5RPB1
6RPC1
7RPD1
4RPA1
O
–
Receive Clock Output (RCLK), port 1
PC(1:4).RPC(3:0) = 1111
B. Default setting after reset
Receive clock output RCLK. After reset RCLK is configured
to be internally pulled up weekly. By setting of PC5.CRP
RCLK is an active output.
RCLK source and frequency selection is made by
CMR1.RS(1:0) if GPC6.COMP_DIS = 0
B or by
CMR4.RS(2:0) if GPC6.COMP_DIS = 1
B.
5RPB1
6RPC1
7RPD1
14
RPA2
I/O
PU/–
Receive Multifunction Pins A to D, port 2
Depending on programming of bits PC(1:4).RPC(3:0) these
multifunction ports carry information to the system interface
or from the system to the QuadFALC
TM. After reset these
ports are configured to be inputs. With the selection of the
appropriate pin function, the corresponding input/output
configuration is achieved automatically. Depending on bit
SIC3.RESR latching/transmission of data is done with the
rising or falling edge of SCLKR. If not connected, an internal
pullup transistor ensures a high input level.
The input function must not be selected twice or more.
Selectable pin functions as described for port 1.
15
RPB2
16
RPC2
17
RPD2
22
RPA3
I/O
PU/–
Receive Multifunction Pins A to D, port 3
Depending on programming of bits PC(1:4).RPC(3:0) these
multifunction ports carry information to the system interface
or from the system to the QuadFALC
TM. After reset these
ports are configured to be inputs. With the selection of the
appropriate pin function, the corresponding input/output
configuration is achieved automatically. Depending on bit
SIC3.RESR latching/transmission of data is done with the
rising or falling edge of SCLKR. If not connected, an internal
pullup transistor ensures a high input level.
The input function must not be selected twice or more.
Selectable pin functions as described for port 1.
23
RPB3
24
RPC3
25
RPD3
Table 1
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No.
Name
Pin Type
Buffer
Type
Function