參數(shù)資料
型號： NS32FV16-25
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 數(shù)字信號處理
英文描述： Advanced Imaging/Communication Signal Processors
中文描述： 16-BIT, 50 MHz, MIXED DSP, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 94/102頁
文件大?。?/td> 1053K
代理商： NS32FV16-25
Appendix B: Instruction Execution Times
(Continued)
TEX Calculation:
Operand 1 is in a register, operand 2 is in memory. This
means that we have to use the table values for the
k
FM
l
case.
The following parameter values are obtained from Table B-2
and the equations in the previous sections.
TEA2 (Absolute Mode)
e
4
TOPD (Memory Write)
e
7 (Operand aligned, no waits)
Tf
e
4
TCY
e
32
TPR
e
TEA2
a
6
e
4
a
6
e
10
From the FPU Execution Timing table in the NS32181 data
sheet we get a TFPU for MOVLF of 19 clock cycles.
The higher value between TPR and TFPU
a
3 is 22. The
total execution time in clock cycles is:
TEX
e
TEA2
a
TOPD
a
TF
a
TCY
a
22
e
65
EXAMPLE 2
Calculate TEX for the instruction MULF 20(R0), 4(10(FP))
Assumptions:
#
The FPU being used is the NS32181.
#
20(R0) is an aligned read with one wait state.
#
10(FP) is an aligned read with no wait states.
#
4(10 (FP)) is an unaligned rmw with two wait states.
TEX Calculation:
Operand 1 and operand 2 are both in memory. Therefore,
the table values for the
k
MM
l
case must be used.
The parameter values obtained from Table B-2 and the
equations in the previous sections are as follows:
(Register Relative Mode)
e
5
TEA2
(Memory Relative Mode)
e
8
a
TOPD
e
15
(TOPD
e
7 (Operand Aligned, No Wait))
TOPD
1
(Read from GEN1)
e
7
a
2
e
9 (Operand
Aligned, One Wait)
TOPD
2
(RMW from GEN2)
e
11
a
6
e
17 (Operand Una-
ligned, Two Waits)
T
f
e
4
TCY
e
22
x
28
TPR
e
0
From the FPU Execution Timing Table in the NS32181 data
sheet we get a TFPU for MULF of 33 clock cycles.
The higher value between TPR and TFPU
a
3 is 36. The
total execution time in clock cycles is:
TEX
e
TEA1
a
TEA2
a
TOPD
1
a
TOPD
2
a
3
#
f
a
TCY
a
36
e
5
a
15
a
9
a
17
a
(22
28)
a
36
e
133
x
140
TEA1
TABLE B-1. Basic Instructions
Mnemonic
Y
TEA1
Y
TEA2
Y
TOPB
Y
TOPW
Y
TOPD
Y
TOPi
Y
L
TCY
Notes
ABSi
1
1
1
1
D
D
D
D
D
D
2
2
D
D
9
8
SCR
k
0
SCR
l
0
ACBi
1
1
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
2
2
D
D
D
D
D
D
16
k
M
l
no branch
k
M
l
branch
k
R
l
no branch
k
R
l
branch
15%20
18
17%22
ADDi
1
1
D
1
D
D
D
D
D
D
D
D
D
D
D
3
1
D
D
D
D
3
4
4
k
xM
l
k
MR
l
k
RR
l
ADDCi
1
1
D
1
D
D
D
D
D
D
D
D
D
D
D
3
1
D
D
D
D
3
4
4
k
xM
l
k
MR
l
k
RR
l
ADDPi
1
1
1
1
D
D
D
D
D
D
3
3
D
D
16
18
No Carry
Carry
ADDQi
D
D
1
D
D
D
D
D
D
D
2
D
D
D
6
4
k
M
l
k
R
l
ADDR
1
1
1
D
D
D
D
D
1
D
D
D
D
D
2
3
k
xM
l
k
xR
l
ADJSPi
1
D
D
D
D
1
D
6
ANDi
1
1
D
1
D
D
D
D
D
D
D
D
D
D
D
3
1
D
D
D
D
3
4
4
k
xM
l
k
MR
l
k
RR
l
ASHi
1
1
1
D
D
2
D
14
x
45
Bcond
D
D
D
D
D
D
D
D
D
D
D
D
D
D
7
no branch
branch
6%10
BICi
1
1
D
1
D
D
D
D
D
D
D
D
D
D
D
3
1
D
D
D
D
3
4
4
k
xM
l
k
MR
l
k
RR
l
94
相關(guān)PDF資料
PDF描述
NS32FX164-25 Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器)
NS32FX161-15 Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器)
NS32FX161-20 Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器)
NS32FX164V-15 Advanced Imaging/Communication Signal Processors
NS32FX164V-20 Advanced Imaging/Communication Signal Processors
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