參數(shù)資料
型號(hào): NS32FV16-25
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類(lèi): 數(shù)字信號(hào)處理
英文描述: Advanced Imaging/Communication Signal Processors
中文描述: 16-BIT, 50 MHz, MIXED DSP, PQCC68
封裝: PLASTIC, LCC-68
文件頁(yè)數(shù): 84/102頁(yè)
文件大小: 1053K
代理商: NS32FV16-25
4.0 Device Specifications
(Continued)
TL/EE/11267–51
Note 1:
ADS must be deactivated before state T4 of the external DMA controller cycle.
Note 2:
During an external DMA cycle WAIT1–2 must be kept inactive unless they are monitored by the DMA Controller. An external DMA cycle is similar to a CPU
cycle. The NS32FX164 generates TSO, RD, WR, ALE and DBE. The external DMA controller drives the address/data lines HBE, ADS and DDIN.
Note 3:
During an external DMA cycle, if the ADS signal is pulsed in order to initiate a bus cycle, the HOLD signal must remain asserted until state T4 of the DMA
cycle.
FIGURE 4-9. External DMA Controller Bus Cycle
84
相關(guān)PDF資料
PDF描述
NS32FX164-25 Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器)
NS32FX161-15 Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器)
NS32FX161-20 Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器)
NS32FX164V-15 Advanced Imaging/Communication Signal Processors
NS32FX164V-20 Advanced Imaging/Communication Signal Processors
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