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| 型號(hào)： | NS32FV16-25 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Advanced Imaging/Communication Signal Processors |
| 中文描述： | 16-BIT, 50 MHz, MIXED DSP, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 29/102頁 |
| 文件大?。?/td> | 1053K |
| 代理商： | NS32FV16-25 |
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3.0 Functional Description
(Continued)
The Operand class columns give the Access Class for each
general operand, defining how the addressing modes are
interpreted (see Series 32000 Instruction Set Reference
Manual).
The Operand Issued columns show the sizes of the oper-
ands issued to the Floating-Point Unit by the CPU. ‘‘D’’ indi-
cates a 32-bit Double Word. ‘‘i’’ indicates that the instruction
specifies an integer size for the operand (B
e
Byte,
W
e
Word, D
e
Double Word). ‘‘f’’ indicates that the in-
struction specifies a Floating-Point size for the operand
(F
e
32-bit Standard Floating, L
e
64-bit Long Floating).
The Returned Value Type and Destination column gives the
size of any returned value and where the CPU places it. The
PSR Bits Affected column indicates which PSR bits, if any,
are updated from the Slave Processor Status Word (Figure
3-3).
TL/EE/11267–12
FIGURE 3-3. Slave Processor Status Word
Any operand indicated as being of type ‘‘f’’ will not cause a
transfer if the Register addressing mode is specified. This is
because the Floating-Point Registers are physically on the
Floating-Point Unit and are therefore available without CPU
assistance.
3.2 EXCEPTION PROCESSING
Exceptions are special events that alter the sequence of
instruction execution. The CPU recognizes two basic types
of exceptions: interrupts and traps.
An interrupt occurs in response to an event generated either
internally, by the on-chip DSP Module, or externally, by acti-
vating NMI or INT. External interrupts are typically request-
ed by peripheral devices that require the CPU’s attention.
Traps occur as a result either of exceptional conditions
(e.g., attempted division by zero) or of specific instructions
whose purpose is to cause a trap to occur (e.g., supervisor
call instruction).
When an exception is recognized, the CPU saves the PC,
PSR and optionally the MOD register contents on the inter-
rupt stack and then it transfers control to an exception serv-
ice procedure.
Details on the operations performed in the various cases by
the CPU to enter and exit the exception service procedure
are given in the following sections.
It is to be noted that the reset operation is not treated here
as an exception. Even though, like any exception, it alters
the instruction execution sequence.
The reason being that the CPU handles reset in a signifi-
cantly different way than it does for exceptions.
Refer to Section 3.5.4 for details on the reset operation.
3.2.1 Exception Acknowledge Sequence
When an exception is recognized, the CPU goes through
three major steps:
1. Adjustment of Registers. Depending on the source of the
exception, the CPU may restore and/or adjust the con-
tents of the Program Counter (PC), the Processor Status
Register (PSR) and the currently-selected Stack Pointer
(SP). A copy of the PSR is made, and the PSR is then set
to reflect Supervisor Mode and selection of the Interrupt
Stack. Trap (TRC) always disabled. Maskable interrupts
are also disabled if the exception is caused by an inter-
rupt.
2. Vector Acquisition. A vector is either obtained from an
external interrupt control unit or is supplied internally by
default.
3. Service Call. The CPU performs one of two sequences
common to all exceptions to complete the acknowledge
process and enter the appropriate service procedure.
The selection between the two sequences depends on
whether the Direct-Exception mode is disabled or en-
abled.
Direct-Exception Mode Disabled
The Direct-Exception mode is disabled while the DE bit in
the CFG register is 0 (Section 2.1.4). In this case the CPU
first pushes the saved PSR copy along with the contents of
the MOD and PC registers on the interrupt stack. Then it
reads the double-word entry from the Interrupt Dispatch ta-
ble at address ‘‘INTBASE’’
a
vector
c
4’’. SeeFigures 3-4
and3-5. The CPU uses this entry to call the exception serv-
ice procedure, interpreting the entry as an external proce-
dure descriptor.
A new module number is loaded into the MOD register from
the least-significant word of the descriptor, and the static-
base pointer for the new module is read from memory and
loaded into the SB register. Then the program-base pointer
for the new module is read from memory and added to the
most-significant word of the module descriptor, which is in-
terpreted as an unsigned value. Finally, the result is loaded
into the PC register.
Direct-Exception Mode Enabled
The Direct-Exception mode is enabled when the DE bit in
the CFG register is set to 1. In this case the CPU first
pushes the saved PSR copy along with the contents of the
PC register on the Interrupt Stack. The word stored on the
Interrupt Stack between the saved PSR and PC register is
reserved for future use; its contents are undefined. The CPU
then reads the double-word entry from the Interrupt Dis-
patch Table at address ‘‘INTBASE
a
vector
c
4’’. The
CPU uses this entry to call the exception service procedure,
interpreting the entry as an absolute address that is simply
loaded into the PC register.Figure 3-6 provides a pictorial of
the acknowledge sequence. It is to be noted that while the
direct-exception mode is enabled, the CPU can respond
more quickly to interrupts and other exceptions because
fewer memory references are required to process an excep-
tion. The MOD and SB registers, however, are not initialized
before the CPU transfers control to the service procedure.
Consequently, the service procedure is restricted from exe-
cuting any instructions, such as CXP, that use the contents
of the MOD or SB registers in effective address calcula-
tions.
29
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