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| 型號： | NS32FV16-25 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Advanced Imaging/Communication Signal Processors |
| 中文描述： | 16-BIT, 50 MHz, MIXED DSP, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 41/102頁 |
| 文件大?。?/td> | 1053K |
| 代理商： | NS32FV16-25 |
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3.0 Functional Description
(Continued)
The CPU core interface specifies the mapping of the DSPM
internal RAM as a contiguous block within the CPU core’s
address space, thus making it possible for normal CPU in-
structions to access and manipulate data and commands in
the DSPM internal RAM (see Section 3.4.4.2). In addition,
the CPU core interface contains control and status registers
that are needed to synchronize the execution of CPU core
instructions concurrently with execution of the DSPM com-
mand lists (see Section 3.4.4.1).
3.4.2 RAM Organization and Data Types
The DSPM internal RAM is organized as a word or double-
word addressable, uniform, linear address space. Memory
locations are numbered sequentially, starting at 0 for the
first location, and incremented by 1 for each successive lo-
cation. The content of each memory location is a 16-bit
word. Double-words must be aligned to an even address.
Valid RAM addresses for access by the command-list exe-
cution unit are 0 through 0x7FF. Access to memory loca-
tions out of the DSMP RAM boundary are not allowed.
The organization of the DSPM internal RAM is shown be-
low:
15
0
Location 0
Location 1
. . .
Locationn
. . .
The RAM array is not restricted to use by the DSPM, it can
also be accessed by the core with any type of memory ac-
cess (e.g., byte, word, or double-word accesses aligned to
any byte address).
The internal RAM stores command lists to be executed, and
data to be manipulated during program execution. Com-
mand lists consist of 16-bit commands, so that each individ-
ual command occupies one memory location.
Each data item is represented as having either a 16-bit or a
32-bit value, as follows:
#
Integer values (16-bit)
#
Aligned-integer values (32-bit)
#
Real values (16-bit)
#
Aligned-real values (32-bit)
#
Extended-precision real values (32-bit)
#
Complex values (32-bit)
3.4.2.1 Integer Values
Integer values are represented as signed 16-bit binary num-
bers in 2’s complement format. The range of integer values
is from
b
2
15
(
b
32768) through 2
15
b
1 (32767). Bit 0 is
the Least Significant Bit (LSB), and bit 15 is the Most Signifi-
cant Bit (MSB).
15
0
Integer Value
Integer values are typically used for addressing vector oper-
ands and for lookup-table index manipulations.
3.4.2.2 Aligned-Integer Values
Aligned-integer values are represented as pairs of integer
values, and must be aligned on a double-word boundary.
The less significant half represents one integer vector ele-
ment, and must be contained in an even-numbered memory
location. The more significant half represents the next vec-
tor element, and must be contained in the next (odd-num-
bered) memory location.
15
0
Integer Value (Low)
(Location 2n )
Integer Value (High)
(Location 2n
a
1)
Aligned-integer values are used for higher throughput in op-
erations where two sequential integer vector elements can
be used in a single iteration. Both elements of an aligned-in-
teger value have the same range and accuracy as specified
for integer values above.
3.4.2.3 Real Values
Real values are represented as 16-bit signed fixed-point
fractional numbers, in 2’s complement format. Bit 15 (MSB)
is the sign bit. Bits 0 (LSB) through 14 represent the frac-
tional part. The binary digit is assumed to lie between bits 14
and 15.
15
0
Real Value
Real values are used to represent samples of analog sig-
nals, coefficients of filters, energy levels, and similar contin-
uous quantities that can be represented using 16-bit accura-
cy. The range of real values is from
b
1.0 (represented as
0x8000
) through 1.0
b
2
b
15
(represented as
0x7FFF
).
3.4.2.4 Aligned-Real Values
Aligned-real values are represented as pairs of real values,
and they must be aligned on a double-word boundary. The
less significant half represents one real vector element, and
must be contained in an even-numbered memory location.
The more significant half represents the next vector ele-
ment, and must be contained in the next (odd-numbered)
memory location.
15
0
Real Value (Low)
(Location 2n )
Real Value (High)
(Location 2n
a
1)
Aligned-real values are used for higher throughput in opera-
tions where two sequential real vector elements can be
used in a single iteration. Both elements of an aligned-real
value have the same range and accuracy as specified for
real values above.
3.4.2.5 Extended-Precision Real Values
Extended-precision real values are represented as 32-bit
signed fixed-point fractional numbers, in 2’s complement
format. Extended-precision real values must be aligned on a
double-word boundary, so that the less significant half is
contained in an even-numbered memory location, and the
more significant half is contained in the next (odd-num-
bered) memory location. Bit 15 (MSB) of the more signifi-
cant part is the sign bit. Bits from 0 (LSB) of the less signifi-
cant part, through 14 of the more significant part, are used
to represent the fractional part. The binary digit is assumed
to lie between bits 14 and 15 of the more significant part.
When extended-precision values are loaded or stored in the
accumulator, bits 1 through 31 of the extended-precision
argument are loaded or stored in bits 0 through 30 of the
41
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