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參數(shù)資料
| 型號(hào)： | NS32FV16-25 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Advanced Imaging/Communication Signal Processors |
| 中文描述： | 16-BIT, 50 MHz, MIXED DSP, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 72/102頁 |
| 文件大?。?/td> | 1053K |
| 代理商： | NS32FV16-25 |
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4.0 Device Specifications
(Continued)
BPU
BPU Cycle.
This signal is activated during a bus cycle to en-
able an external BITBLT processing unit. The
EXTBLT instruction activates this signal.
Note:
BPU is low (Active) only during bus cycles involving pre-
fetching instructions and execution of EXTBLT oper-
ands. It is recommended that BPU, ADS and status lines
(ST0–ST3) be used to qualify BPU bus cycles. If a DMA
circuit exists in the system, the HLDA signal should be
used to further qualify BPU cycles. BPU may become
active during T4 of a non-BPU bus cycle, and may be-
come inactive during T4 of a BPU bus cycle. BPU must
be qualified by ADS and status lines (ST0–ST3) to be
used as an external gating signal.
RSTO
Reset Output.
This signal becomes active when RSTI is low,
initiating a system reset.
RD
Read Strobe.
Activated during CPU or DMA read cycles to en-
able reading of data from memory or peripherals.
See Section 3.5.5.2.
WR
Write Strobe.
Activated during CPU or DMA write cycles to en-
able writing of data to memory or peripherals.
TSO
Timing State Output.
The falling edge of TSO identifies the beginning
of state T2 of a bus cycle. The rising edge identi-
fies the beginning of state T4.
DBE
Data Buffers Enable.
Used to control external data buffers. It is active
when the data buffers are to be enabled.
OSCOUT Crystal Output.
This line is used as the return path for the crystal
(if used). When an external clock source is used,
OSCOUT should be left unconnected or loaded
with no more than 5 pF of stray capacitance.
IAS
Special Cycle Address Strobe.
Signals the beginning of a special bus cycle.
CTTL1–2 System Clock.
Output clock for bus timing. CTTL1 and CTTL2
must be externally connected together.
FCLK
Fast Clock.
This clock is derived from the clock waveform on
OSCIN. Its frequency is either the same as
OSCIN or is lower, depending upon the scale fac-
tor programmed into the CFG register.
ALE
Address Latch Enable.
Active high signal that can be used to control
external address latches.
IOUT
Interrupt Output
Activated when the execution of a command list
stops and the associated interrupt is enabled.
4.1.4 Input-Output Signals
*
Address/Data Bus.
AD0–15
Multiplexed Address/Data Information. Bit 0 is
the least significant bit of each.
SPC
Slave Processor Control.
Used by the CPU as the data strobe output for
slave processor transfers; used by a slave proc-
essor to acknowledge completion of a slave in-
struction. See Section 3.5.5.7.
*
Data Direction.
Status signal indicating the directon of the data
transfer during a bus cycle. During HOLD ac-
knowledge this signal becomes an input and de-
termines the activation of RD or WR.
*
Address Strobe
Controls address latches; signals the beginning
of a bus cycle. During HOLD acknowledge this
signal becomes an input and the CPU monitors it
to detect the beginning of a DMA cycle and gen-
erate the relevant strobe signals. When a DMA is
used, ADS should be pulled up to V
CC
through a
10 k
X
resistor.
DDIN
ADS
72
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