參數(shù)資料
型號(hào)： NS32FV16-25
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 數(shù)字信號(hào)處理
英文描述： Advanced Imaging/Communication Signal Processors
中文描述： 16-BIT, 50 MHz, MIXED DSP, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 48/102頁
文件大小： 1053K
代理商： NS32FV16-25
3.0 Functional Description
(Continued)
Syntax:
EXEC DJNZ
15
11 10
0
10000
101 0110 1100
Note:
Accumulator is not affected.
DBPTDDebug Breakpoint
The DBPT instruction is used for implementing software de-
bug breakpoint in the DSPM command-list. Whenever there
is an attempt to execute a DBPT instruction, the NMIS-
TAT.UND bit is set to ‘‘1’’.
Syntax:
EXEC DBPT
15
11 10
0
10000
111 1111 1110
Note:
Accumulator is not affected.
3.4.5.8 Internal Memory Move Instructions
VRMOVDVector Real Move
The VRMOV instruction copies the real X vector to the real
Z vector.
Syntax:
EXEC VRMOV
15
11 10
0
10000
101 0010 1011
Operation:
à
real X, Z;
for (n
4
0; n
k
LENG; n
00
)
à
Z
[
n
] 4
X
[
n
]
;
ó
ó
VARMOVDVector Aligned Real Move
The VARMOV instruction copies the aligned real X vector to
the aligned real Z vector.
Syntax:
EXEC VARMOV
15
11 10
0
10000
100 0011 1000
Operation:
à
aligned real X, Z;
for (n
4
0; n
k
LENG; n
00
)
à
Z
[
n
]
.low
4
X
[
n
]
.low;
Z
[
n
]
.high
4
X
[
n
]
.high;
ó
ó
VRGATHDVector Real Gather
The VRGATH instruction gathers non-contiguous elements
of the X real vector, as specified by the Y integer vector, and
places them in contiguous locations in the Z real vector.
Syntax:
EXEC VRGATH
15
11 10
0
10000
100 0011 1010
Operation:
à
real X, Z;
integer X.ADDR, Y;
for (n
4
0; n
k
LENG; n
00
)
à
Z
[
n
] 4
mem
[
(X.ADDR
0
Y
[
n
]
) & 0xFFFF
]
;
ó
ó
VRSCATDVector Real Scatter
The VRSCAT instruction scatters contiguous elements of
the X real vector, and places them in non-contiguous loca-
tions in the Z real vector, as specified by the Y integer vec-
tor.
Syntax:
EXEC VRSCAT
15
11 10
0
10000
100 0100 0000
Operation:
à
real X, Z;
integer Z.ADDR, Y;
for (n
4
0; n
k
LENG; n
00
)
à
mem
[
Z.ADDR
0
Y
[
n
]
) & 0xFFFF
] 4
X
[
n
]
;
ó
ó
3.4.5.9 External Memory Move Instructions
VXLOADDVector External Load
The VXLOAD instruction loads a vector from external mem-
ory into the Z vector. The external memory address is speci-
fied in the EABR and X registers.
Syntax:
EXEC VXLOAD
15
11 10
0
10000
100 0100 1111
Operation:
VXLOAD
à
real X, Z;
ext address EABR;
for (n
4
0; n
k
LENG; n
00
)
à
Z
[
n
] 4
ext mem
[
EABR
0
(ext address)
2
*
&X
[
n
]]
ó
ó
VXSTOREDVector External Store
The VXSTORE instruction stores the Z vector into an exter-
nal memory vector. The external memory address is speci-
fied in the EABR and X registers.
48
相關(guān)PDF資料
PDF描述
NS32FX164-25 Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器)
NS32FX161-15 Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器)
NS32FX161-20 Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器)
NS32FX164V-15 Advanced Imaging/Communication Signal Processors
NS32FX164V-20 Advanced Imaging/Communication Signal Processors
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NS32FX100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
NS32FX100-15 制造商:NSC 制造商全稱:National Semiconductor 功能描述:System Controller
NS32FX100VF 制造商:NSC 制造商全稱:National Semiconductor 功能描述:System Controller
NS32FX16 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
NS32FX161 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
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