參數(shù)資料
型號： NS32FV16-25
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 數(shù)字信號處理
英文描述： Advanced Imaging/Communication Signal Processors
中文描述： 16-BIT, 50 MHz, MIXED DSP, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 51/102頁
文件大?。?/td> 1053K
代理商： NS32FV16-25
3.0 Functional Description
(Continued)
Operation:
à
aligned integer X,Y;
integer Z;
for (n
4
0; n
k
LENG; n
00
)
à
Z
[
2n
] 4
(integer) (Z
[
2n
] 0
X
[
n
]
.low *
Y
[
n
]
.low);
Z
[
2n
0
1
] 4
(integer) (Z
[
2n
0
1
] 0
X
[
n
]
.high
* Y
[
n
]
.high);
ó
ó
Note:
When PARAM.CLR is set to ‘‘1’’, only multiplication is done without
addition. When PARAM.SUB is set to ‘‘1’’, the ‘‘
a
’’ sign is replaced
by a ‘‘
b
’’ sign.
VAIMADSDVector Aligned Integer Multiply and Add
Saturated
The VAIMADS instruction multiplies corresponding ele-
ments of the X and Y integer vectors, and adds or subtracts
the result, as an integer value, to the integer vector Z. This
result is placed in the Z output vector. The saturation logic
provides clamping of the accumulator results before writing
the result back to the Z vector whenever the result cannot
be represented correctly within the limits of the integer data
type.
Syntax:
EXEC VAIMADS
15
11 10
0
10000
101 0101 1100
Operation:
à
aligned integer X,Y;
integer Z;
for (n
4
0; n
k
LENG; n
00
)
à
Z
[
2n
]
4
(integer) (Z
[
2n
] 0
X
[
n
]
.low *
Y
[
n
]
.low);
Z
[
2n
0
1
]
4
(integer) (Z
[
2n
0
1
] 0
X
[
n
]
.high *
Y
[
n
]
.high);
ó
ó
VRMADDVector Real Multiply and Add
The VRMAD instruction multiplies corresponding elements
of the X and Y real vectors and adds or subtracts the result
to the real vector Z. This result is placed in the Z output
vector.
Syntax:
EXEC VRMAD
15
11 10
0
10000
100 0011 0011
Operation:
à
real X,Y,Z;
for (n
4
0; n
k
LENG; n
00
)
à
Z
[
n
] 4
(real) (Z
[
n
] 0
X
[
n
]
* Y
[
n
]
);
ó
ó
Note:
When PARAM.CLR is set to ‘‘1’’, only multiplication is performed,
without addition. When PARAM.SUB is set to ‘‘1’’, the ‘‘
a
’’ sign is
replaced by a ‘‘
b
’’ sign.
VARMADDVector Aligned Real Multiply and Add
The VARMAD instruction multiplies corresponding elements
of the X and Y real vectors and adds or subtracts the result
to the real vector Z. This result is placed in the Z output
vector.
Syntax:
EXEC VARMAD
15
11 10
0
10000
100 0000 1110
Operation:
à
aligned real X,Y,Z;
for (n
4
0; n
k
LENG; n
00
)
à
Z
[
n
]
.low
4
(real) (Z
[
n
]
.low
0
X
[
n
]
.low *
Y
[
n
]
.low);
Z
[
n
]
.high
4
(real) (Z
[
n
]
.high
0
X
[
n
]
.high
* Y
[
n
]
.high);
ó
ó
Note:
When PARAM.CLR is set to ‘‘1’’, only multiplication is performed,
without addition. When PARAM.SUB is set to ‘‘1’’, the ‘‘
a
’’ sign is
replaced by a ‘‘
b
’’ sign.
VEMADDVector Extended Multiply and Add
The VEMAD instruction multiplies corresponding elements
of the X and Y real vectors and adds or subtracts the result,
as an extended-precision value, to the extended-precision
vector Z. This result is placed in the Z output vector.
Syntax:
EXEC VEMAD
15
11 10
0
10000
101 0001 0010
51
相關(guān)PDF資料
PDF描述
NS32FX164-25 Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器)
NS32FX161-15 Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器)
NS32FX161-20 Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器)
NS32FX164V-15 Advanced Imaging/Communication Signal Processors
NS32FX164V-20 Advanced Imaging/Communication Signal Processors
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NS32FX100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
NS32FX100-15 制造商:NSC 制造商全稱:National Semiconductor 功能描述:System Controller
NS32FX100VF 制造商:NSC 制造商全稱:National Semiconductor 功能描述:System Controller
NS32FX16 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
NS32FX161 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
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