- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄363665 > NS32FV16-25 (NATIONAL SEMICONDUCTOR CORP) Advanced Imaging/Communication Signal Processors PDF資料下載
參數(shù)資料
| 型號(hào)： | NS32FV16-25 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Advanced Imaging/Communication Signal Processors |
| 中文描述： | 16-BIT, 50 MHz, MIXED DSP, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 64/102頁 |
| 文件大小： | 1053K |
| 代理商： | NS32FV16-25 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁當(dāng)前第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁
3.0 Functional Description
(Continued)
3.5.5.5 Interrupt Control Cycles
Activating the INT or NMI pin on the CPU will initiate one or
more bus cycles whose purpose in interrupt control rather
than the tranfer of instructions or data. Execution of the
Return from Interrupt Instruction (RETI) will also cause In-
terrupt Control bus cycles. These differ from instruction or
data transfers only in the status presented on pins ST0–
ST3. All Interrupt Control cycles are single-byte Read cy-
cles.
Table 3-4 shows the Interrupt Control sequences associat-
ed with each interrupt and with the return from its service
routine. For full details of the NS32FX164 interrupt struc-
ture, see Section 3.2.
TABLE 3-4. Interrupt Sequences
Cycle
Status
Address
DDIN
HBE
A0
High Bus
Low Bus
A. Non-Maskable Interrupt Control Sequence
Interrupt Acknowledge
1
0100
FFFF00
16
0
1
0
Don’t Care
Don’t Care
Interrupt Return
None: Performed through Return from Trap (RETT) instruction.
B. Non-Vectored Interrupt Control Sequence
Interrupt Acknowledge
1
0100
FFFE00
16
0
1
0
Don’t Care
Don’t Care
Interrupt Return
None: Performed through Return from Trap (RETT) instruction.
C. Vectored Interrupt Sequence: Non-Cascaded
Interrupt Acknowledge
1
0100
FFFE00
16
0
1
0
Don’t Care
Vector:
Range: 0–127
Interrupt Return
1
0110
FFFE00
16
0
1
0
Don’t Care
Vector: Same as
in Previous Int.
Ack. Cycle
D. Vectored Interrupt Sequence: Cascaded
Interrupt Acknowledge
1
0100
FFFE00
16
0
1
0
Don’t Care
Cascade Index:
range
b
16 to
b
1
(The CPU here uses the Cascade Index to find the Cascade Address.)
2
0101
Cascade
Address
0
1 or
0
*
0 or
1
*
Vector, range 0–255; on appropriate
half or Data Bus for even/odd
address
Interrupt Return
1
0110
FFFE00
16
0
1
0
Don’t Care
Cascade Index:
same as in
previous Int.
Ack. Cycle
(The CPU here uses the Cascade Index to find the Cascade Address.)
2
0111
Cascade
Address
0
1 or
0
*
0 or
1
*
Don’t Care
Don’t Care
*
If the Cascaded ICU Address is Even (A0 is low), then the CPU applies HBE high and reads the vector number from bits 0–7 of the Data Bus.
If the address is Odd (A0 is high), then the CPU applies HBE low and reads the vector number from bits 8–15 of the Data Bus. The vector number may be in the
range 0–225.
64
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NS32FX164-25 | Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號(hào)處理器) |
| NS32FX161-15 | Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號(hào)處理器) |
| NS32FX161-20 | Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號(hào)處理器) |
| NS32FX164V-15 | Advanced Imaging/Communication Signal Processors |
| NS32FX164V-20 | Advanced Imaging/Communication Signal Processors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NS32FX100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| NS32FX100-15 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:System Controller |
| NS32FX100VF | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:System Controller |
| NS32FX16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| NS32FX161 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。