參數(shù)資料
型號: NS32FV16-25
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 數(shù)字信號處理
英文描述: Advanced Imaging/Communication Signal Processors
中文描述: 16-BIT, 50 MHz, MIXED DSP, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 66/102頁
文件大?。?/td> 1053K
代理商: NS32FV16-25
3.0 Functional Description
(Continued)
TL/EE/11267–37
Note:
CPU samples Data Bus here.
FIGURE 3-25. Slave Processor Read Cycle
The CPU does not pulse the Address Strobe (ADS), and no
bus signals are generated. The direction of a transfer is de-
termined by the sequence (‘‘protocol’’) established by the
instruction under execution; but the CPU indicates the direc-
tion on the DDIN pin for hardware debugging purposes.
A Slave Processor operand is transferred in one or more
Slave bus cycles. A Byte operand is transferred on the
least-significant byte of the Data Bus (AD0–AD7), and a
Word operand is transferred on the entire bus. A Double
Word is transferred in a consecutive pair of bus cycles,
least-significant word first. A Quad Word is transferred in
two pairs of Slave cycles, with other bus cycles possibly
occurring between them. The word order is from least-signif-
icant word to most-significant.
Figure 3-27 shows the NS32FX164 and FPU connection di-
agram.
66
相關(guān)PDF資料
PDF描述
NS32FX164-25 Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器)
NS32FX161-15 Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器)
NS32FX161-20 Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器)
NS32FX164V-15 Advanced Imaging/Communication Signal Processors
NS32FX164V-20 Advanced Imaging/Communication Signal Processors
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