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參數(shù)資料
| 型號： | NS32829 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 1 Megabit High Speed Dynamic RAM Controller/Drivers |
| 中文描述： | 1兆位動態(tài)隨機存儲器的高速控制器/驅(qū)動器 |
| 文件頁數(shù)： | 9/26頁 |
| 文件大小： | 481K |
| 代理商： | NS32829 |
DP8428/DP8429 Mode Descriptions
(Continued)
MODE 1–AUTOMATIC FORCED REFRESH
In Mode 1 the R/C (RFCK) pin becomes RFCK (refresh
cycle clock) and the CASIN (RGCK) pin becomes RGCK
(RAS generator clock). If RFCK is high and Mode 1 is en-
tered then the chip operates as if in MODE 0 (externally
controlled refresh), with all RAS outputs following RASIN.
This feature of Mode 1 may be useful for those who want to
use Mode 5 (automatic access) with externally controlled
refresh. By holding RFCK permanently high one need only
toggle M2 (RFSH) to switch from Mode 5 to external re-
fresh. As with Mode 0, RFI/O may be pulled low by an ex-
ternal gate to reset the refresh counter.
When using Mode 1 as automatic refresh, RFCK must be an
input clock signal. One refresh should occur each period of
RFCK. If no refresh is performed while RFCK is high, then
when RFCK goes low RFI/O immediately goes low to indi-
cate that a refresh is requested. (RFI/O may still be used to
reset the refresh counter even though it is also used as a
refresh request pin, however, an open-collector gate should
be used to reset the counter in this case since RFI/O is
forced low internally for a request).
After receiving the refresh request the system must allow a
forced refresh to take place while RFCK is low. External
logic can monitor RFRQ (RFI/O) so that when RFRQ goes
low this logic will wait for the access currently in progress to
be completed before pulling M2 (RFSH) low to put the
DP8429 in mode 1. If no access is taking place when RFRQ
occurs, then M2 may immediately go low. Once M2 is low,
the refresh counter contents appear at the address outputs
and RAS is generated to perform the refresh.
An external clock on RGCK is required to derive the refresh
RAS signals. On the second falling edge of RGCK after M2
is low, all RAS lines go low. They remain low until two more
falling edges of RGCK. Thus RAS remains high for one to
two periods of RGCK after M2 goes low, and stays low for
two periods. In order to obtain the minimum delay from M2
going low to RAS going low, M2 should go low t
RFSRG
be-
fore the falling edge of RGCK.
The Refresh Request on RFI/O is terminated as RAS goes
low. This signal may be used to end the refresh earlier than
it normally would as described above. If M2 is pulled high
TL/F/8649–15
j
RFCK goes low
k
RFRQ goes low if no hidden refresh
occurred while RFCK was high
l
Next RASIN starts next access
m
m
P acknowledges refresh request
n
Forced refresh RAS starts after
l
T
(
l
t
RP
)
o
Forced refresh RAS ends RFRQ
p
m
P removes refresh acknowledge
FIGURE 3. DP8428/DP8429 Performing a Forced Refresh (Mode 5
x
1
x
5) with Various Microprocessors
9
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