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參數(shù)資料
| 型號： | NS32829 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 1 Megabit High Speed Dynamic RAM Controller/Drivers |
| 中文描述： | 1兆位動態(tài)隨機存儲器的高速控制器/驅動器 |
| 文件頁數(shù)： | 21/26頁 |
| 文件大?。?/td> | 481K |
| 代理商： | NS32829 |
Switching Characteristics: DP8428 and DP8429
(Continued)
V
CC
e
5.0V
g
10%, 0
§
C
s
T
A
s
70
§
C unless otherwise noted (Notes 2, 4, 5), the output load capacitance is typical for 4
banks of 22 DRAMs each or 88 DRAMs, including trace capacitance.
*
These values are Q0-Q9, C
L
e
500 pF; RAS0–RAS3, C
L
e
150 pF; WE, C
L
e
500 pF; CAS, C
L
e
600 pF; RL
e
500
X
unless otherwise noted. See Figure 11 for test load. Maximum propagation delays are specified with all outputs
switching.
**
Preliminary
Symbol
Access Parameter
Condition
*
CL
**
All C
L
e
50 pF
Min
Units
Min
Max
Max
t
RCDL1
RAS to CAS Low Delay
(RAHS
e
1)
RAS to CAS Low Delay
(RAHS
e
1)
RAS to CAS High Delay
Figure 6
DP8428-80/29-80
34
63
ns
t
RCDL1
Figure 6
DP8428-70/29-70
34
55
ns
t
RCDH
t
RAH0
Figure 6
22
ns
Row Address Hold Time
(RAHS
e
0, Mode 5)
Row Address Hold Time
(RAHS
e
1, Mode 5)
Column Address Set-up Time
(Mode 5)
Figure 6
25
25
ns
t
RAH1
Figure 6
15
15
ns
t
ASC
Figure 6
0
0
ns
t
RCV0
RASIN to Column Address
Valid (RAHS
e
0, Mode 5)
RASIN to Column Address
Valid (RAHS
e
0, Mode 5)
RASIN to Column Address
Valid (RAHS
e
1, Mode 5)
RASIN to Column Address
Valid (RAHS
e
1, Mode 5)
RASIN to RAS Low Delay
Figure 6
DP8428-80/29-80
94
ns
t
RCV0
Figure 6
DP8428-70/29-70
85
ns
t
RCV1
Figure 6
DP8428-80/29-80
76
ns
t
RCV1
Figure 6
DP8428-70/29-70
68
ns
t
RPDL
t
RPDH
t
ASRL
t
APD
Figures 5a, 5b, 6
21
18
ns
RASIN to RAS High Delay
Figures 5a, 5b, 6
20
17
ns
Address Set-up to RASIN low
Figures 5a, 5b, 6
13
ns
Address Input to Output
Delay
Figures 5a, 5b, 6
36
25
ns
t
SPD
Address Strobe High to
Address Output Valid
Figures 5a, 5b
48
ns
t
ASA
t
AHA
t
ADS
t
WPD
t
CPDL
Address Set-up Time to ADS
Figures 5a, 5b, 6
5
ns
Address Hold Time from ADS
Figures 5a, 5b, 6
10
ns
Address Strobe Pulse Width
Figures 5a, 5b, 6
26
ns
WIN to WE Output Delay
Figure 5b
28
ns
CASIN to CAS Low Delay
(R/C low, Mode 4)
Figure 5b
17
33
ns
t
CPDH
CASIN to CAS High Delay
(R/C low, Mode 4)
Figure 5b
13
33
ns
t
CPdif
t
CPDL
- t
CPDH
See Mode 4
Description
13
ns
t
RCC
Column Select to Column
Address Valid
Figure 5a
41
ns
t
RCR
Row Select to Row
Address Valid
Figures 5a, 5b
45
ns
t
RHA
Row Address Held from
Column Select
Figure 5a
7
ns
t
CCAS
R/C Low to CAS Low Delay
(CASIN Low, Mode 4)
Figure 5a
DP8428-80/29-80
50
ns
t
CCAS
R/C Low to CAS Low Delay
(CASIN Low, Mode 4)
Figure 5a
DP8428-70/29-70
46
ns
t
DIF1
Maximum (t
RPDL
- t
RHA
)
See Mode 4
Description
7
ns
t
DIF2
Maximum (t
RCC
- t
CPDL
)
13
ns
21
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