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參數(shù)資料
| 型號： | NS32829 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 1 Megabit High Speed Dynamic RAM Controller/Drivers |
| 中文描述： | 1兆位動態(tài)隨機(jī)存儲器的高速控制器/驅(qū)動器 |
| 文件頁數(shù)： | 20/26頁 |
| 文件大?。?/td> | 481K |
| 代理商： | NS32829 |
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Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage, V
CC
Storage Temperature Range
7.0V
b
65
§
C to
a
150
§
C
Input Voltage
5.5V
Output Current
150 mA
300
§
C
Lead Temp. (Soldering, 10 seconds)
Operating Conditions
Min
4.50
Max
5.50
Units
V
V
CC
T
A
Supply Voltage
Ambient
Temperature
0
a
70
§
C
Electrical Characteristics
V
CC
e
5.0V
g
10%, 0
§
C
s
T
A
s
70
§
C unless otherwise noted (Note 2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
C
I
IH
I
I
RSI
I
IL1
I
IL2
V
IL
V
IH
V
OL1
V
OL2
V
OH1
V
OH2
I
1D
I
0D
I
CC
*
Except RFI/O
**
Except RFI/O, ADS, R/C, CS, M2, RASIN
Input Clamp Voltage
V
CC
e
Min, I
C
e b
12 mA
V
IN
e
2.5V
V
IN
e
0.5V, Output high
V
IN
e
0.5V
V
IN
e
0.5V
b
0.8
b
1.2
V
Input High Current for all Inputs
2.0
100
m
A
Output Load Current for RFI/O
Input Low Current for all Inputs
**
b
0.7
b
0.02
b
0.05
b
1.5
b
0.25
b
0.5
mA
mA
ADS, R/C, CS, M2, RASIN
mA
Input Low Threshold
0.8
V
Input High Threshold
Output Low Voltage
*
2.0
V
I
OL
e
20 mA
I
OL
e
8 mA
I
OH
e b
1 mA
I
OH
e b
100
m
A
V
OUT
e
0.8V (Note 3)
V
OUT
e
2.4V (Note 3)
V
CC
e
Max
0.3
0.5
V
Output Low Voltage for RFI/O
Output High Voltage
*
0.3
0.5
V
2.4
3.5
V
Output High Voltage for RFI/O
Output High Drive Current
*
Output Low Drive Current
*
2.4
3.5
V
b
50
b
200
mA
50
200
mA
Supply Current
150
240
mA
Switching Characteristics: DP8428 and DP8429
V
CC
e
5.0V
g
10%, 0
§
C
s
T
A
s
70
§
C unless otherwise noted (Notes 2, 4, 5), the output load capacitance is typical for 4
banks of 22 DRAMs each or 88 DRAMs, including trace capacitance.
*
These values are Q0-Q9, C
L
e
500 pF; RAS0–RAS3, C
L
e
150 pF; WE, C
L
e
500 pF; CAS, C
L
e
600 pF; RL
e
500
X
unless otherwise noted. See Figure 11 for test load. Maximum propagation delays are specified with all outputs
switching.
**
Preliminary
Symbol
Access Parameter
Condition
*
CL
**
All C
L
e
50 pF
Units
Min
Max
Min
Max
t
RICL0
RASIN to CAS Low Delay
(RAHS
e
0)
Figure 6
DP8428-80/29-80
57
97
42
85
ns
t
RICL0
RASIN to CAS Low Delay
(RAHS
e
0)
Figure 6
DP8428-70/29-70
57
87
42
75
ns
t
RICL1
RASIN to CAS Low Delay
(RAHS
e
1)
Figure 6
DP8428-80/29-80
48
80
35
68
ns
t
RICL1
RASIN to CAS Low Delay
(RAHS
e
1)
Figure 6
DP8428-70/29-70
48
70
35
58
ns
t
RICH
t
RCDL0
RASIN to CAS High Delay
Figure 6
37
ns
RAS to CAS Low Delay
(RAHS
e
0)
Figure 6
DP8428-80/29-80
43
80
ns
t
RCDL0
RAS to CAS Low Delay
(RAHS
e
0)
Figure 6
DP8428-70/29-70
43
72
ns
20
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