- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄363665 > NS32829 (National Semiconductor Corporation) 1 Megabit High Speed Dynamic RAM Controller/Drivers PDF資料下載
參數(shù)資料
| 型號： | NS32829 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 1 Megabit High Speed Dynamic RAM Controller/Drivers |
| 中文描述： | 1兆位動態(tài)隨機存儲器的高速控制器/驅動器 |
| 文件頁數(shù)： | 10/26頁 |
| 文件大?。?/td> | 481K |
| 代理商： | NS32829 |
DP8428/DP8429 Mode Descriptions
(Continued)
while the RAS lines are low, then the RASs go high t
RFRH
later. The designer must be careful, however, not to violate
the minimum RAS low time of the DRAMs. He must also
guarantee that the minimum RAS precharge time is not vio-
lated during a transition from mode 1 to mode 5 when an
access is desired immediately following a refresh.
If the processor tries to access memory while the DP8429 is
in mode 1, WAIT states should be inserted into the proces-
sor cycles until the DP8429 is back in mode 5 and the de-
sired access has been accomplished (see Figure 9).
Instead of using WAIT states to delay accesses when re-
freshing, HOLD states could be used as follows. RFRQ
could be connected to a HOLD or Bus Request input to the
system. When convenient, the system acknowledges the
HOLD or Bus Request by pulling M2 low. Using this
scheme, HOLD will end as the RAS lines go low (RFI/O
goes high). Thus, there must be sufficient delay from the
time HOLD goes high to the DP8429 returning to mode 5, so
that the RAS low time of the DRAMs isn’t violated as de-
scribed earlier (see Figure 3 for mode 1 refresh with Hold
states).
To perform a forced refresh the system will be inactive for
about four periods of RGCK. For a frequency of 10 MHz,
this is 400 ns. To refresh 128 rows every 2 ms an average of
about one refresh per 16
m
s is required. With a RFCK period
of 16
m
s and RGCK period of 100 ns, DRAM accesses are
delayed due to refresh only 2.5% of the time. If using the
Hidden Refresh available in mode 5 (refreshing with RFCK
high) this percentage will be even lower.
MODE 4 - EXTERNALLY CONTROLLED ACCESS
In this mode all control signal outputs can be controlled
directly by the corresponding control input. The enabled
RAS output follows RASIN, CAS follows CASIN (with R/C
low), WE follows WIN and R/C determines whether the row
or the column inputs are enabled to the address outputs
(see Figure 4).
With R/C high, the row address latch contents are enabled
onto the address bus. RAS going low strobes the row ad-
dress into the DRAMs. After waiting to allow for sufficient
row-address hold time (t
RAH
) after RAS goes low, R/C can
go low to enable the column address latch contents onto
the address bus. When the column address is valid, CAS
going low will strobe it into the DRAMs. WIN determines
whether the cycle is a read, write or read-modify-write ac-
cess. Refer toFigures 5a and5b for typical Read and Write
timing using mode 4.
Page or Nibble mode may be performed by toggling CASIN
once the initial access has been completed. In the case of
page mode the column address must be changed before
*
Resistors required depends on DRAM load.
DRAMs Maybe 16k, 64k, 256k, 1M
For 4 Banks, can drive 16 data bits
a
6 Check Bits for ECC.
For 2 Banks, can drive 32 data bits
a
7 Check Bits for ECC.
For 1 Bank, can drive 64 data bits
a
8 Check Bits for ECC.
TL/F/8649–16
FIGURE 4. Typical Application of DP8429 Using External Control Access and Refresh in Modes 0 and 4
10
相關PDF資料 |
PDF描述 |
|---|---|
| NS32FX16-15 | FILM/M CAPACITANCE=0.001 VOLT=630 |
| NS32FX16-20 | Imaging/Signal Processor |
| NS32FX16-25 | Imaging/Signal Processor |
| NS32FX164-20 | Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器) |
| NS32FV16-25 | Advanced Imaging/Communication Signal Processors |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| NS32829D-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NS32829D-70/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NS32829D-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NS32829D-80/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NS32829V-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
發(fā)布緊急采購，3分鐘左右您將得到回復。