參數(shù)資料
型號(hào)： NS32829
廠商： National Semiconductor Corporation
英文描述： 1 Megabit High Speed Dynamic RAM Controller/Drivers
中文描述： 1兆位動(dòng)態(tài)隨機(jī)存儲(chǔ)器的高速控制器/驅(qū)動(dòng)器
文件頁(yè)數(shù)： 6/26頁(yè)
文件大?。?/td> 481K
代理商： NS32829
Pin Definitions
(Continued)
B0, B1: Bank Select Inputs –
These pins are decoded to
enable one or two of the four RAS outputs during an access
(see Table I and Table II).
TABLE I. DP8429 Memory Bank Decode
Bank Select
(Strobed by ADS)
Enabled RAS
n
B1
B0
0
0
1
1
0
1
0
1
RAS
0
RAS
1
RAS
2
RAS
3
TABLE II. DP8428 Memory Bank Decode
Bank Select
(Strobed by ADS)
Enabled RAS
n
B1
NC
0
1
X
X
RAS
0
& RAS
1
RAS
2
& RAS
3
Conditions for All Modes
INPUT ADDRESSING
The address block consists of a row-address latch, a col-
umn-address latch, and a resettable refresh counter. The
address latches are fall-through when ADS is high and latch
when ADS goes low. If the address bus contains valid ad-
dresses until after CAS goes low at the end of the memory
cycle, ADS can be permanently high. Otherwise ADS must
go low while the addresses are still valid.
DRIVE CAPABILITY
The DP8429 has timing parameters that are specified driv-
ing the typical capacitance (including traces) of 88, 5V-only
DRAMs. Since there are 4 RAS outputs, each is specified
driving one-fourth of the total memory. CAS, WE and the
address outputs are specified driving all 88 DRAMs.
The graph inFigure 10 may be used to determine the slight
variations in timing parameters, due to loading conditions
other than 88 DRAMs.
Because of distributed trace capacitance and inductance
and DRAM input capacitance, current spikes can be creat-
ed, causing overshoots and undershoots at the DRAM in-
puts that can change the contents of the DRAMs or even
destroy them. To reduce these spikes, a damping resistor
(low inductance, carbon) should be inserted between the
DP8429 outputs and the DRAMs, as close as possible to
the DP8429. The damping resistor values may differ de-
pending on how heavily an output is loaded. These resistors
should be determined by the first prototypes (not wire-
wrapped due to the larger distributed capacitance and in-
ductance). Resistors should be chosen such that the tran-
sition on the control outputs is critically damped. Typical
values will be from 15
X
to 100
X
, with the lower values be-
ing used with the larger memory arrays. Note that AC pa-
rameters are specified with 15
X
damping resistors. For
more information see AN-305 ‘‘Precautions to Take When
Driving Memories’’.
DP8429 DRIVING ANY 256k or 1M DRAMS
The DP8429 can drive any 256k or 1M DRAMs. 256k
DRAMs require 18 of the DP8429’s address inputs to select
one memory location within the DRAM. RAS-only refreshing
with the nine-bit refresh-counter on the DP8429 makes CAS
before RAS refreshing, available on 256k DRAMs, unneces-
sary (see Figure 1a).
1 Mbit DRAMs require the use of all 10 of the DP8429 Ad-
dress Outputs (see Figure 1b).
READ, WRITE AND READ-MODIFY-WRITE CYCLES
The output signal, WE, determines what type of memory
access cycle the memory will perform. If WE is kept high
while CAS goes low, a read cycle occurs. If WE goes low
before CAS goes low, a write cycle occurs and data at DI
(DRAM input data) is written into the DRAM as CAS goes
low. If WE goes low later than t
CWD
after CAS goes low, first
a read occurs and DO (DRAM output data) becomes valid,
then data DI is written into the same address in the DRAM
as WE goes low. In this read-modify-write case, DI and DO
cannot be linked together. WE always follows WIN directly
to determine the type of access to be performed.
POWER-UP INITIALIZE
When V
CC
is first applied to the DP8429, an initialize pulse
clears the refresh counter and the internal control flip-flops.
Mode Features Summary
Y
4 modes of operation: 2 access and 2 refresh
Y
Automatic or external selected by the user
Y
Auto access mode provides RAS, row to column
change, and then CAS automatically.
Y
Choice between two different values of t
RAH
in auto-ac-
cess mode
Y
CAS controlled independently in external control mode,
allowing for nibble mode accessing
Y
Automatic refreshing can make refreshes transparent to
the system
Y
CAS is inhibited during refresh cycles
6
相關(guān)PDF資料
PDF描述
NS32FX16-15 FILM/M CAPACITANCE=0.001 VOLT=630
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NS32FX16-25 Imaging/Signal Processor
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