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參數(shù)資料
| 型號(hào)： | NS32829 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 1 Megabit High Speed Dynamic RAM Controller/Drivers |
| 中文描述： | 1兆位動(dòng)態(tài)隨機(jī)存儲(chǔ)器的高速控制器/驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 15/26頁 |
| 文件大?。?/td> | 481K |
| 代理商： | NS32829 |
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DP8428/DP8429 Mode Descriptions
(Continued)
TL/F/8649–23
FIGURE 7b. Typical Application of DP8429 Using Modes 5 and 1
Applications
If one desires a memory interface containing the DP8429
that minimizes the number of external components required,
modes 5 and 1 should be used. These two modes provide:
1) Automatic access to memory (in mode 5 only one signal,
RASIN, is required in order to access memory)
2) Hidden refresh capability (refreshes are performed auto-
matically while in mode 5 when non-local accesses are
taking place, as determined by CS)
3) Refresh request capability (if no hidden refresh took
place while RFCK was high, a refresh request is generat-
ed at the RFI/O pin when RFCK goes high)
4) Automatic forced refresh (If a refresh request is generat-
ed while in mode 5, as described above, external logic
should switch the DP8429 into mode 1 to do an automat-
ic forced refresh. No other external control signals need
be issued. WAIT states can be inserted into the proces-
sor machine cycles if the system tries to access memory
while the DP8429 is in mode 1 doing a forced refresh).
Some items to be considered when integrating the DP8429
into a system design are:
1) The system designer should ensure that a DRAM access
not be in progress when a refresh mode is entered. Simi-
larly, one should not attempt to start an access while a
refresh is in progress. The parameter t
RFHRL
specifies
the minimum time from RFSH high to RASIN going low to
initiate an access.
2) One should always guarantee that the DP8429 is enabled
for access prior to initiating the access (see t
CSRL1
).
3) One should bring RASIN low even during non-local ac-
cess cycles when in mode 5 in order to maximize the
chance of a hidden refresh occurring.
4) At lower frequencies (under 10 Mhz), it becomes increas-
ingly important to differentiate between READ and
WRITE cycles. RASIN generation during READ cycles
can take place as soon as one knows that a processor
READ access cycle has started. WRITE cycles, on the
other hand, cannot start until one knows that the data to
be written at the DRAM inputs will be valid a setup time
before CAS (column address strobe) goes true at the
DRAM inputs. Therefore, in general, READ cycles can be
initiated earlier than WRITE cycles.
5) Many times it is possible to only add WAIT states during
READ cycles and have no WAIT states during WRITE
cycles. This is because it generally takes less time to
write data into memory than to read data from memory.
15
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