參數(shù)資料
型號(hào)： NS32829
廠商： National Semiconductor Corporation
英文描述： 1 Megabit High Speed Dynamic RAM Controller/Drivers
中文描述： 1兆位動(dòng)態(tài)隨機(jī)存儲(chǔ)器的高速控制器/驅(qū)動(dòng)器
文件頁(yè)數(shù)： 14/26頁(yè)
文件大?。?/td> 481K
代理商： NS32829
DP8428/DP8429 Mode Descriptions
(Continued)
Once it is started, a hidden refresh will continue even if
RFCK goes low. However, CS must be high throughout the
refresh (until RASIN goes high).
These hidden refreshes are valuable in that they do not
delay accesses. When determining the duty cycle of RFCK,
the high time should be maximized in order to maximize the
probability of hidden refreshes. If a hidden refresh doesn’t
happen, then a refresh request will occur on RFI/O when
RFCK goes low. After receiving the request, the system
must perform a refresh while RFCK is low. This may be
done by going to mode 1 and allowing an automatic refresh
(see mode 1 description). This refresh must be completed
while RFCK is low, thus the RFCK low time is determined by
the worst-case time required by the system to respond to a
refresh request.
(c)
Mode 5 Refresh (Hidden Refresh) with mode 0 Refresh
(External Refresh)
This refresh scheme is identical to that in (b) except that
after receiving a refresh request, mode 0 is entered to do
the refresh (see mode 0 description). The refresh request is
terminated (RFI/O goes high) as soon as mode 0 is en-
tered. This method requires more control than using mode 1
(auto-refresh), however, it may be desirable if the mode 1
refresh time is considered to be excessive.
Example
Figure 7b demonstrates how a system designer would use
the DP8429 in mode 5 based on certain characteristics of
his system.
System Characteristics:
1) DRAM used has min t
RAH
requirement of 15 ns and
min t
ASR
of 0 ns
2) DRAM address is valid from time T
V
to the end of the
memory cycle
3) four banks of twenty-two 256k memory chips each are
being driven
Using the DP8429 (see Figure 7b):
1) Tie pin 4 (RAHS) high to guarantee a 15 ns minimum
t
RAH
which is sufficient for the DRAMs being used
2) Generate RASIN no earlier than time T
V
a
t
ASRL
(see
switching characteristics), so that the row address is
valid on the DRAM address inputs before RAS occurs
3) Tie ADS high since latching the DRAM address on the
DP8429 is not necessary
4) Connect the first 20 system address bits to R0-R9 and
C0-C9, and bits 21 and 22 to B0 and B1
5) Connect each RAS output of the DP8429 to the RAS
inputs of the DRAMs of one bank of the memory array;
connect Q0-Q9 of the DP8429 to A0-A9 of all DRAMs;
connect CAS of the DP8429 to CAS of all the DRAMs
Figure 7c illustrates a similar example using the DP8428 to
drive two 32-bit banks.
TL/F/8649–22
FIGURE 7a. Hidden Refreshing (Mode 5) and Forced Refreshing (Mode 1) Timing
14
相關(guān)PDF資料
PDF描述
NS32FX16-15 FILM/M CAPACITANCE=0.001 VOLT=630
NS32FX16-20 Imaging/Signal Processor
NS32FX16-25 Imaging/Signal Processor
NS32FX164-20 Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器)
NS32FV16-25 Advanced Imaging/Communication Signal Processors
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NS32829D-70 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller
NS32829D-70/A+ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller
NS32829D-80 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller
NS32829D-80/A+ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller
NS32829V-70 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller
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