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參數(shù)資料
| 型號： | NS32829 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 1 Megabit High Speed Dynamic RAM Controller/Drivers |
| 中文描述： | 1兆位動態(tài)隨機存儲器的高速控制器/驅(qū)動器 |
| 文件頁數(shù)： | 2/26頁 |
| 文件大?。?/td> | 481K |
| 代理商： | NS32829 |
General Description
(Continued)
With its four independent RAS outputs and ten multiplexed
address outputs, the DP8429 can support up to four banks
of 64k, 256k or 1M DRAMs. Two bank select pins, B1 and
B0, are decoded to activate one of the RAS signals during
an access, leaving the three non-selected banks in the
standby mode (less than one tenth of the operating power)
with data outputs in TRI-STATE
é
. The DP8428’s one Bank
Select pin, B1, enables 2 banks automatically during an ac-
cess in order to provide an optimum interface for 32-bit mi-
croprocessors.
The DP8428 and DP8429 each have two mode-select pins,
allowing for two refresh modes and two access modes. Re-
fresh and access timing may be controlled either externally
or automatically. The automatic modes require a minimum
of input control signals.
A refresh counter is on-chip and is multiplexed with the row
and column inputs. Its contents appear at the address out-
puts of the DP8428 or DP8429 during any refresh, and are
incremented at the completion of the refresh. Row, Column
and bank address latches are also on-chip. However, if the
address inputs to the DP8428 or DP8429 are valid through-
out the duration of the access, these latches may be operat-
ed in the fall-through mode.
Each device is available in either the 52 pin Ceramic DIP, or
the low cost JEDEC standard 68 pin Plastic Chip Carrier
(PCC) package.
Functional Block Diagrams
DP8429
TL/F/8649–2
2
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相關代理商/技術參數(shù) |
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| NS32829D-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NS32829D-70/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NS32829D-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NS32829D-80/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NS32829V-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
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