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參數資料
| 型號： | NS32829 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 1 Megabit High Speed Dynamic RAM Controller/Drivers |
| 中文描述： | 1兆位動態(tài)隨機存儲器的高速控制器/驅動器 |
| 文件頁數： | 22/26頁 |
| 文件大?。?/td> | 481K |
| 代理商： | NS32829 |
Switching Characteristics: DP8428 and DP8429
(Continued)
V
CC
e
5.0V
g
10%, 0
§
C
s
T
A
s
70
§
C unless otherwise noted (Notes 2, 4, 5). The output load capacitance is typical for 4
banks of 22 DRAMs each or 88 DRAMs, including trace capacitance.
*
These values are Q0-Q9, C
L
e
500 pF; RAS0–RAS3, C
L
e
150 pF; WE, C
L
e
500 pF; CAS, C
L
e
600 pF; RL
e
500
X
unless otherwise noted. See Figure 11 for test load. Maximum propagation delays are specified with all outputs
switching.
**
Preliminary
Symbol
Refresh Parameter
Condition
*
CL
**
All C
L
e
50 pF
Units
Min
Max
Min
Max
t
RC
Refresh Cycle Period
Figure 2a
100
ns
t
RASINL,H
Pulse Width of RASIN
during Refresh
Figure 2a
50
ns
t
RFPDL0
RASIN to RAS Low Delay
during Refresh (Mode 0)
Figure 2a
28
ns
t
RFPDL5
RASIN to RAS Low Delay
during Hidden Refresh
Figure 7
38
ns
t
RFPDH0
RASIN to RAS High Delay
during Refresh (Mode 0)
Figure 2a
35
ns
t
RFPDH5
RASIN to RAS High Delay
during Hidden Refresh
Figure 7
44
ns
t
RFLCT
RFSH Low to Counter
Address Valid
Figures 2a, 3
CS
e
X
38
ns
t
RFLRL
RFSH Low Set-up to RASIN
Low (Mode 0), to get
Minimum t
ASR
e
0
Figure 2a
12
ns
t
RFHRL
RFSH High Setup to Access
RASIN Low
Figure 3
25
ns
t
RFHRV
RFSH High to Row
Address Valid
Figure 3
43
ns
t
ROHNC
RAS High to New Count
Valid
Figure 2a
42
ns
t
RST
Counter Reset Pulse Width
Figure 2a
60
ns
t
CTL
RFI/O Low to Counter
Outputs All Low
Figure 2a
100
ns
t
RFCKL,H
Minimum Pulse Width
of RFCK
Figure 7
100
ns
T
Period of RAS Generator
Clock
Figure 3
30
ns
t
RGCKL
Minimum Pulse Width Low
of RGCK
Figure 3
15
ns
t
RGCKH
Minimum Pulse Width High
of RGCK
Figure 3
15
ns
t
FRQL
RFCK Low to Forced RFRQ
(RFI/O) Low
Figure 3
C
L
e
50 pF
RL
e
35k
66
ns
t
FRQH
RGCK Low to Forced RFRQ
High
Figure 3
C
L
e
50 pF
RL
e
35k
55
ns
22
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