參數(shù)資料
型號(hào)： NS32829
廠商： National Semiconductor Corporation
英文描述： 1 Megabit High Speed Dynamic RAM Controller/Drivers
中文描述： 1兆位動(dòng)態(tài)隨機(jī)存儲(chǔ)器的高速控制器/驅(qū)動(dòng)器
文件頁(yè)數(shù)： 12/26頁(yè)
文件大小： 481K
代理商： NS32829
DP8428/DP8429 Mode Descriptions
(Continued)
CASIN goes low to access a new memory location (see
Figure 5c). Parameter t
CPdif
has been specified in order that
users may easily determine minimum CAS pulse widths
when CASIN is toggling.
AUTOMATIC CAS GENERATION
CAS is held high when R/C is high even if CASIN is low. If
CASIN is low when R/C goes low, CAS goes low automati-
cally, t
ASC
after the column address is valid. This feature
eliminates the need for an externally derived CASIN signal
to control CAS when performing a simple access (Figure 5a
demonstrates Auto-CAS generation in mode 4). Page or nib-
ble accessing may be performed as shown in Figure 5c
even if CAS is generated automatically for the initial access.
FASTEST MEMORY ACCESS
The fastest Mode 4 access is achieved by using the auto-
matic CAS feature and external delay line to generate the
required delay between RASIN and R/C. The amount of
delay required depends on the minimum t
RAH
of the DRAMs
being used. The DP8429 parameter t
DIF1
has been speci-
fied in order that the delay between RASIN and R/C may be
minimized.
t
DIF1
e
MAXIMUM (t
RPDL
- t
RHA
)
where t
RPDL
e
RASIN to RAS delay
and t
RHA
e
row address held from R/C going low.
The delay between RASIN and R/C that guarantees the
specified DRAM t
RAH
is given by
MINIMUM RASIN to R/C
e
t
DIF1
a
t
RAH
.
Example
In an application using DRAMs that require a minimum t
RAH
of 15 ns, the following demonstrates how the maximum
RASIN to CAS time is determined.
With t
DIF1
(from Switching Characteristics)
e
7 ns,
RASIN to R/C delay
e
7 ns
a
15 ns
e
22 ns.
A delay line of 25 ns will be sufficient.
With Auto-CAS generation, the maximum delay from R/C to
CAS (loaded with 600 pF) is 46 ns. Thus the maximum
RASIN to CAS time is 71 ns, under the given conditions.
With a maximum RASIN to RAS time (t
RPDL
) of 20 ns, the
maximum RAS to CAS time is about 51 ns. Most DRAMs
with a 15 ns minimum t
RAH
have a maximum t
RCD
of about
60 ns. Thus memory accesses are likely to be RAS limited
instead of CAS limited. In other words, memory access time
is limited by DRAM performance, not controller perform-
ance.
REFRESHING IN CONJUNCTION WITH MODE 4
If using mode 4 to access memory, mode 0 (externally con-
trolled refresh) must be used for all refreshing.
MODE 5 – AUTOMATIC ACCESS WITH HIDDEN RE-
FRESHING CAPABILITY
Automatic-Access has two advantages over the externally
controlled access (mode 4). First, RAS, CAS and the row to
column change are all derived internally from one input sig-
nal, RASIN. Thus the need for an external delay line (see
mode 4) is eliminated.
Secondly, since R/C and CASIN are not needed to gener-
ate the row to column change and CAS, these pins can be
used for the automatic refreshing function.
AUTOMATIC ACCESS CONTROL
Mode 5 of the DP8429 makes accessing Dynamic RAM
nearly as easy as accessing static RAM. Once row and col-
umn addresses are valid (latched on the DP8429 if neces-
sary), RASIN going low is all that is required to perform the
memory access.
TL/F/8649–19
FIGURE 5c. Page or Nibble Access in Mode 4
12
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