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參數(shù)資料
| 型號(hào)： | NS32829 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 1 Megabit High Speed Dynamic RAM Controller/Drivers |
| 中文描述： | 1兆位動(dòng)態(tài)隨機(jī)存儲(chǔ)器的高速控制器/驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 7/26頁 |
| 文件大?。?/td> | 481K |
| 代理商： | NS32829 |
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DP8428/DP8429 Mode Descriptions
MODE 0–EXTERNALLY CONTROLLED REFRESH
Figure 2 shows the Externally Controlled Refresh timing. In
this mode the refresh counter contents are multiplexed to
the address outputs. All RAS outputs are enabled to follow
RASIN so that the row address indicated by the refresh
counter is refreshed in all DRAM banks when RASIN goes
low. The refresh counter increments when RASIN goes
high. RFSH should be held low at least until RASIN goes
high (they may go high simultaneously) so that the refresh
address remains valid and all RAS outputs remain enabled
throughout the refresh.
A burst refresh may be performed by holding RFSH low and
toggling RASIN until all rows are refreshed. It may be useful
in this case to reset the refresh counter just prior to begin-
ning the refresh. The refresh counter resets to all zeroes
when RFI/O is pulled low by an external gate. The refresh
counter always counts to 511 before rolling over to zero. If
there are 128 or 256 rows being refreshed then Q7 or Q8,
respectively, going high may be used as an end-of-burst
indicator.
In order that the refresh address is valid on the address
outputs prior to the RAS lines going low, RFSH must go low
before RASIN. The setup time required is given by t
RFLRL
in
the Switching Characteristics. This parameter may be ad-
justed using Figure 10 for loading conditions other than
those specified.
TABLE III. DP8428/DP8429 Mode Select Options
Mode
(RFSH)
M2
M0
Mode of Operation
0
0
0
Externally Controlled
Refresh
Auto Refresh–Forced
Externally Controlled
Access
Auto Access
(Hidden Refresh)
1
4
0
1
1
0
5
1
1
DP8428/DP8429 Interface Between System and DRAM Banks
TL/F/8649–12
All 9 Bits of Refresh Counter Used
FIGURE 1a. DP8428/DP8429 with 256k DRAMs
TL/F/8649–25
All 9 Bits of Refresh Counter Used
FIGURE 1b. DP8428/DP8429 with 1M DRAMs
7
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| NS32829D-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NS32829D-70/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NS32829D-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NS32829D-80/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NS32829V-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
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