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參數(shù)資料
| 型號： | MT9VDDT1672A |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | DDR SDRAM DIMM |
| 中文描述： | DDR SDRAM的內(nèi)存 |
| 文件頁數(shù)： | 24/29頁 |
| 文件大?。?/td> | 542K |
| 代理商： | MT9VDDT1672A |
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128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
24
2003 Micron Technology. Inc.
NOTE:
1. The SPD EEPROM WRITE cycle time (
t
WRC) is the time from a valid stop condition of a write sequence to the end of
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
Table 18: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to V
SS
; V
DDSPD
= +2.3V to +3.6V
PARAMETER/CONDITION
SYMBOL
V
DD
V
IH
V
IL
V
OL
I
LI
I
LO
I
SB
MIN
3
MAX
3.6
UNITS
V
V
V
V
μA
μA
μA
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
OUTPUT LOW VOLTAGE: IOUT = 3mA
INPUT LEAKAGE CURRENT: VIN = GND to VDD
OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD
STANDBY CURRENT:
SCL = SDA = VDD - 0.3V; All other inputs = V
SS
or V
REF
POWER SUPPLY CURRENT:
SCL clock frequency = 100 KHz
V
DD
x 0.7 V
DD
+ 0.5
-1
–
–
–
–
V
DD
x 0.3
0.4
10
10
30
I
CC
–
2
mA
Table 19: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to V
SS
; V
DDSPD
= +2.3V to +3.6V
PARAMETER/CONDITION
SYMBOL
MIN
0.3
MAX
3.5
UNITS
μs
NOTES
SCL LOW to SDA data-out valid
t
AA
t
BUF
t
DH
t
F
t
HD:DAT
t
HD:STA
t
HIGH
t
I
t
LOW
t
R
t
SCL
t
SU:DAT
t
SU:STA
t
SU:STO
t
WRC
Time the bus must be free before a new transition can start
4.7
μs
Data-out hold time
300
ns
SDA and SCL fall time
300
ns
Data-in hold time
0
μs
Start condition hold time
4
μs
Clock HIGH period
4
μs
Noise suppression time constant at SCL, SDA inputs
100
ns
Clock LOW period
4.7
μs
SDA and SCL rise time
1
μs
SCL clock frequency
100
KHz
Data-in setup time
250
ns
Start condition setup time
4.7
μs
Stop condition setup time
4.7
μs
WRITE cycle time
10
ms
1
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