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| 型號： | MT9VDDT1672A |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | DDR SDRAM DIMM |
| 中文描述： | DDR SDRAM的內(nèi)存 |
| 文件頁數(shù)： | 20/29頁 |
| 文件大?。?/td> | 542K |
| 代理商： | MT9VDDT1672A |
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128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
20
2003 Micron Technology. Inc.
31. READs and WRITEs with auto precharge are not
allowed to be issued until
t
RAS (MIN) can be satis-
fied prior to the internal precharge command
being issued.
32. Any positive glitch must be less than 1/3 of the
clock cycle and not more than +400mV or 2.9V,
whichever is less. Any negative glitch must be less
than 1/3 of the clock cycle and not exceed either -
300mV or 2.2V, whichever is more positive. The
DC average cannot go below 2.3V minimum.
33. Normal Output Drive Curves:
a)The full variation in driver pull-down current
from minimum to maximum process, tempera-
ture and voltage will lie within the outer bound-
ing lines of the V-I curve of Figure 9, Pull-Down
Characteristics.
b)The variation in driver pull-down current
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I curve
of Figure 9, Pull-Down Characteristics.
c)T
he full variation in driver pull-up current from
minimum to maximum process, temperature and
voltage will lie within the outer bounding lines of
the V-I curve of Figure 10, Pull-Up Characteristics.
d)The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of
Figure 10,
Pull-Up Characteristics
.
e)The full variation in the ratio of the maximum to
minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
f)The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source voltages
from 0.1V to 1.0V.
34. The voltage levels used are derived from a mini-
mum V
DD
level and the refernced test load. In
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
35. V
IH
overshoot: V
IH
(MAX) = V
DD
Q+1.5V for a pulse
width 3ns and the pulse width can not be greater
than 1/3 of the cycle rate. V
IL
undershoot: V
IL
(MIN)
= -1.5V for a pulse width 3ns and the pulse width
can not be greater than 1/3 of the cycle rate.
36. V
DD
and V
DD
Q must track each other.
37. This maximum value is derived from the refer-
enced test load. In practice, the values obtained
in a typical terminated design may reflect up to
310ps less for
t
HZ (MAX) and the last DVW.
t
HZ
(MAX) will prevail over
t
DQSCK (MAX) +
t
RPST
(MAX) condition.
t
LZ (MIN) will prevail over
t
DQSCK (MIN) +
t
RPRE (MAX) condition.
38. For slew rates of greater than 1V/ns the (LZ) tran-
sition will start about 310ps earlier.
39. During initialzation, V
DD
Q, V
TT
, and V
REF
must be
equal to or less than V
DD
+ 0.3V. Alternatively, V
TT
may be 1.35V maximum during power up, even if
V
DD
/V
DD
Q are 0.0V, provided a minimum of 42
ohms of series resistance is used between the V
TT
supply and the input pin.
Figure 9: Pull-Down Characteristics
Figure 10: Pull-Up Characteristics
160
140
I
O
V
OUT
(V)
Nominal low
Minimum
Nominal high
Maximum
120
100
80
60
40
20
0
0.0
0.5
1.0
1.5
2.0
2.5
0
-20
I
O
Nominal low
Minimum
Nominal high
Maximum
-40
-60
-80
-100
-120
-140
-160
-180
-200
0.0
0.5
1.0
1.5
2.0
2.5
V
DD
Q - V
OUT
(V)
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