參數(shù)資料
型號(hào)： MT9VDDT1672A
廠商： Micron Technology, Inc.
英文描述： DDR SDRAM DIMM
中文描述： DDR SDRAM的內(nèi)存
文件頁(yè)數(shù)： 18/29頁(yè)
文件大?。?/td> 542K
代理商： MT9VDDT1672A
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
18
2003 Micron Technology. Inc.
Notes
1. All voltages referenced to V
SS
.
2. Tests for AC timing, I
DD
, and electrical AC and DC
characteristics may be conducted at nominal ref-
erence/supply voltage levels, but the related spec-
ifications and device operation are guaranteed for
the full voltage range specified.
3. Outputs measured with equivalent load:
4. AC timing and I
DD
tests may use a V
IL
-to-V
IH
swing of up to 1.5V in the test environment, but
input timing is still referenced to V
REF
(or to the
crossing point for CK/CK#), and parameter speci-
fications are guaranteed for the specified AC input
levels under normal use conditions. The mini-
mum slew rate for the input signals used to test
the device is 1V/ns in the range between V
IL
(
AC
)
and V
IH
(
AC
).
5. The AC and DC input level specifications are as
defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
6. V
REF
is expected to equal V
DD
Q/2 of the transmit-
ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on V
REF
may not exceed ±2 percent of the
DC value. Thus, from V
DD
Q/2, V
REF
is allowed
±25mV for DC error and an additional ±25mV for
AC noise. This measurement is to be taken at the
nearest V
REF
by-pass capacitor.
7. V
TT
is not applied directly to the device. V
TT
is a
system supply for signal termination resistors, is
expected to be set equal to V
REF
and must track
variations in the DC level of V
REF
.
8. I
DD
is dependent on output loading and cycle
rates. Specified values are obtained with mini-
mum cycle time at CL = 2 for -262, -26A, and -202,
CL = 2.5 for -265 and -335 with the outputs open.
9. Enables on-chip refresh and address counters.
10. I
DD
specifications are tested after the device is
properly initialized, and is averaged at the defined
cycle rate.
11. This parameter is sampled. V
DD
= +2.5V ±0.2V,
V
DD
Q = +2.5V ±0.2V, V
REF
= V
SS
, f = 100 MHz, T
A
=
25°C, V
OUT
(DC) = V
DD
Q/2, V
OUT
(peak to peak) =
0.2V. DM input is grouped with I/O pins, reflecting
the fact that they are matched in loading.
12. Command/Address input slew rate = 0.5V/ns. For
-335 and -262, -26A, and -265 with slew rates 1V/
ns and faster,
t
IS and
t
IH are reduced to 900ps. If
the slew rate is less than 0.5V/ns, timing must be
derated:
t
IS has an additional 50ps per each
100mV/ns reduction in slew rate from the 500mV/
ns.
t
IH has 0ps added, that is, it remains constant.
If the slew rate exceeds 4.5V/ns, functionality is
uncertain.
13. The CK/CK# input reference level (for timing ref-
erenced to CK/CK#) is the point at which CK and
CK# cross; the input reference level for signals
other than CK/CK# is V
REF
.
14. Inputs are not recognized as valid until V
REF
stabi-
lizes. Exception: during the period before V
REF
stabilizes, CKE 0.3 x V
DD
Q is recognized as LOW.
15.
The output timing reference level, as measured at the
timing reference point indicated in Note 3, is V
TT
.
16.
time windows as valid data transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (HZ) or begins driving (LZ).
17.
The maximum limit for this parameter is not a
device limit. The device will operate with a greater
value for this parameter, but system performance
(bus turnaround) will degrade accordingly.
18. This is not a device limit. The device will operate
with a negative value, but system performance
could be degraded due to bus turnaround.
19. It is recommended that DQS be valid (HIGH or
LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on
t
DQSS.
20. MIN (
t
RC or
t
RFC) for I
DD
measurements is the
smallest multiple of
t
CK that meets the minimum
absolute value for the respective parameter. tRAS
(MAX) for Idd measurements is the largest multi-
ple of
t
CK that meets the maximum absolute
value for
t
RAS.
21. The refresh period 64ms. This equates to an aver-
age refresh rate of 15.625μs (128MB module)
7.8125μs (256MB module). However, an AUTO
REFRESH command must be asserted at least
t
HZ and
t
LZ transitions occur in the same access
Output
(V
OUT
)
Reference
Point
30pF
50
V
TT
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