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| 型號： | MT9VDDT1672A |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | DDR SDRAM DIMM |
| 中文描述： | DDR SDRAM的內(nèi)存 |
| 文件頁數(shù)： | 16/29頁 |
| 文件大小： | 542K |
| 代理商： | MT9VDDT1672A |
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128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16
2003 Micron Technology. Inc.
Table 14: Capacitance (All Modules)
Note: 11; notes appear on pages 18–21
PARAMETER
SYMBOL
C
IO
C
I
1
C
I
2
C
I
2
C
I
2
C
I
3
MIN
4.0
2.0
12.0
9
10.5
18.0
MAX
5.0
3.0
15.0
12.0
13.5
27.0
UNITS
pF
pF
pF
pF
pF
pF
Input/Output Capacitance: DQs, DQSs
Input Capacitance: Command and Address, S0#
Input Capacitance: CK0, CK0# (-26A, -265, -202)
Input Capacitance: CK0, CK0# (-335)
Input Capacitance: CK1, CK1#, CK2, CK2# (-26A, -265, -202)
Input Capacitance: CKE
Table 15: Electrical Characteristics and Recommended AC Operating Conditions
Notes: 1–5, 8, 12–15, 29, 31, 50; notes appear on pages 18–21; 0 C T
A
+70 C; V
DD
= V
DD
Q = +2.5V ±0.2V
AC CHARACTERISTICS
-335
-26A/265
-202
UNITS NOTES
ns
PARAMETER
SYMBOL
MIN
-0.7
MAX
+0.7
MIN
-0.75 +0.75
MAX
MIN
-0.8
MAX
+0.8
Access window of DQ from CK/CK#
t
AC
t
CH
t
CL
CK high-level width
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
t
CK
ns
26
CK low-level width
0.45
0.55
0.45
0.55
0.45
0.55
26
Clock cycle time
CL = 2.5
t
CK (2.5)
6
13
7.5
13
8
13
40, 47,
48
40, 47
CL = 2
t
CK (2)
t
DH
t
DS
t
DIPW
t
DQSCK
t
DQSH
t
DQSL
t
DQSQ
7.5
13
7.5
13
10
13
ns
DQ and DM input hold time relative to DQS
0.45
0.5
0.6
ns
23, 27
DQ and DM input setup time relative to DQS
0.45
0.5
0.6
ns
23, 27
DQ and DM input pulse width (for each input)
1.75
1.75
2
ns
27
Access window of DQS from CK/CK#
-0.60
+0.60 -0.75 +0.75
-0.8
+0.8
ns
DQS input high pulse width
0.35
0.35
0.35
t
CK
t
CK
ns
DQS input low pulse width
0.35
0.35
0.35
DQS-DQ skew, DQS to last DQ valid, per group, per
access
Write command to first DQS latching transition
0.45
0.5
0.6
22, 25
t
DQSS
t
DSS
t
DSH
t
HP
t
HZ
t
LZ
t
IH
F
t
IS
F
t
IH
S
t
IS
S
t
MRD
t
QH
0.75
1.25
0.75
1.25
0.75
1.25
t
CK
t
CK
t
CK
ns
DQS falling edge to CK rising - setup time
0.2
0.2
0.2
DQS falling edge from CK rising - hold time
0.2
0.2
0.2
Half clock period
t
CH,
t
CL
t
CH,
t
CL
t
CH,
t
CL
30
Data-out high-impedance window from CK/CK#
+0.70
+0.75
+0.8
ns
16, 37
Data-out low-impedance window from CK/CK#
-0.70
-0.75
-0.8
ns
16, 38
Address and control input hold time (fast slew rate)
0.75
0.90
1.1
ns
12
Address and control input setup time (fast slew rate)
0.75
0.90
1.1
ns
12
Address and control input hold time (slow slew rate)
0.80
1
1.1
ns
12
Address and control input setup time (slow slew rate)
0.80
1
1.1
ns
12
LOAD MODE REGISTER command cycle time
12
15
16
ns
DQ-DQS hold, DQS to first DQ to go non-valid, per
access
Data hold skew factor
t
HP -
t
QHS
t
HP -
t
QHS
t
HP-
t
QHS
ns
22, 23
t
QHS
0.55
0.75
1
ns
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