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| 型號： | MT9VDDT1672A |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | DDR SDRAM DIMM |
| 中文描述： | DDR SDRAM的內(nèi)存 |
| 文件頁數(shù)： | 19/29頁 |
| 文件大?。?/td> | 542K |
| 代理商： | MT9VDDT1672A |
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128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
19
2003 Micron Technology. Inc.
once every 140.6μs (128MB module) or 70.3μs
(256MB module); burst refreshing or posting by
the DRAM controller greater than eight refresh
cycles is not allowed.
22. The valid data window is derived by achieving
other specifications -
t
HP (
t
CK/2), tDQSQ, and
t
QH (
t
QH =
t
HP -
t
QHS). The data valid window
derates directly porportional with the clock duty
cycle and a practical data valid window can be
derived. The clock is allowed a maximum duty
cycle variation of 45/55. Functionality is uncer-
tain when operating beyond a 45/55 ratio. Figure
8, Derating Data Valid Window (
t
QH -
t
DQSQ),
shows the derating curves for duty cycles ranging
between 50/50 and 45/55.
23. Each byte lane has a separate DQS, with DQ0–
DQ7.
24. This limit is actually a nominal value and does not
result in a fail value. CKE is HIGH during
REFRESH command period (
t
RFC [MIN]) else
CKE is LOW (i.e., during standby).
25. To maintain a valid level, the transitioning edge of
the input must:
a)Sustain a constant slew rate from the current AC
level through to the target AC level, V
IL
(AC) or
V
IH
(AC).
b)Reach at least the target AC level.
c)After the AC target level is reached, continue to
maintain at least the target DC level, V
IL
(DC) or
V
IH
(DC)
.
26. CK and CK# input slew rate must be
2V/ns if measured differentially).
27. DQ and DM input slew rates must not deviate
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to
t
DS and
t
DH for each 100mv/ns reduction in slew rate. If
slew rate exceeds 4V/ns, functionality is uncer-
tain.
28. V
DD
must not vary more than 4 percent if CKE is
not active while any device bank is active.
29. The clock is allowed up to ±150ps of jitter. Each
timing parameter is allowed to vary by the same
amount.
30.
minimum actually applied to the device CK and
CK# inputs, collectively during bank active.
1V/ns (
t
HP (MIN) is the lesser of
t
CL minimum and
t
CH
Figure 8: Derating Data Valid Window
(
t
QH -
t
DQSQ)
3.750
3.700
3.650
3.600
3.550
3.500
3.450
3.400
3.350
3.300
3.250
3.400
3.350
3.300
3.250
3.200
3.150
3.100
3.050
3.000
2.950
2.900
2.500
2.463
2.425
2.388
2.350
2.313
2.275
2.238
2.200
2.163
2.125
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
50/50
49.5/50.5
49/51
48.5/52.5
48/52
47.5/53.5
47/53
46.5/54.5
46/54
45.5/55.5
45/55
Clock Duty Cycle
n
-26A/-265 @
t
CK = 10ns
-202 @
t
CK = 10ns
-26A/-265 @
t
CK = 7.5ns
-202 @
t
CK = 8ns
-335 @
t
CK = 6ns
TBD
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9VDDT1672AG-202A1 | 制造商:Micron Technology Inc 功能描述:DRAM MOD DDR SDRAM 1.125GBIT 184UDIMM - Trays |
| MT9VDDT1672AG-265B1 | 制造商:Micron Technology Inc 功能描述:DRAM MOD DDR SDRAM 1.125GBIT 184UDIMM - Trays |
| MT9VDDT1672AG-265D4 | 制造商:Micron Technology Inc 功能描述: |
| MT9VDDT1672AG-26AA1 | 制造商:Micron Technology Inc 功能描述:DRAM MOD DDR SDRAM 1.125GBIT 184UDIMM - Trays |
| MT9VDDT1672AG-26AB1 | 制造商:Micron Technology Inc 功能描述:DRAM MOD DDR SDRAM 1.125GBIT 184UDIMM - Trays |
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