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| 型號： | MT9VDDT1672A |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | DDR SDRAM DIMM |
| 中文描述： | DDR SDRAM的內(nèi)存 |
| 文件頁數(shù)： | 10/29頁 |
| 文件大?。?/td> | 542K |
| 代理商： | MT9VDDT1672A |
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128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
10
2003 Micron Technology. Inc.
reset the DLL, it should always be followed by a LOAD
MODE REGISTER command to select normal operat-
ing mode.
All other combinations of values for A7–A11, or A7–
A12 are reserved for future use and/or test modes. Test
modes and reserved states should not be used because
unknown operation or incompatibility with future ver-
sions may result.
NOTE:
1. For a burst length of two, A1
–
A
i
select the two-
data-element block; A0 selects the first access
within the block.
2. or a burst length of four, A2
–
A
i
select the four-
data-element block; A0
–
A1 select the first access
within the block.
3. For a burst length of eight, A3
–
A
i
select the eight-
data-element block; A0
–
A2 select the first access
within the block.
4. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
5.
i
= 11 for 128MB module,
i
= 12 for 256MB module
Figure 6: CAS Latency Diagram
Extended Mode Register
The extended mode register controls functions
beyond those controlled by the mode register; these
additional functions are DLL enable/disable and out-
put drive strength. These functions are controlled via
the bits shown in Figure 7, Extended Mode Register
Definition Diagram, on page 11. The extended mode
register is programmed via the LOAD MODE REGIS-
TER command to the mode register (with BA0 = 1 and
BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power. The
Table 6:
Burst Definition Table
BURST
LENGTH
STARTING
COLUMN
ADDRESS
ORDER OF ACCESSES WITHIN A
BURST
TYPE =
SEQUENTIAL
TYPE =
INTERLEAVED
2
A0
0
1
0-1
1-0
0-1
1-0
4
A1 A0
0
0
1
1
0
1
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
8
A2 A1 A0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Table 7:
CAS Latency (CL) Table
SPEED
-335
-26A
-265
-202
ALLOWABLE OPERATING
FREQUENCY (MHZ)
CL = 2
N/A
75 f 133
75 f 100
75 f 100
CL = 2.5
75 f 167
75 f 133
75 f 133
75 f 125
CK
CK#
COMMAND
DQ
DQS
CL = 2
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
Burst Length = 4 in the cases shown
Shown with nominal tAC, tDQSCK, and tDQSQ
CK
CK#
COMMAND
DQ
DQS
CL = 2.5
T0
T1
T2
T2n
T3
T3n
T0
T1
T2
T2n
T3
T3n
DON’T CARE
TRANSITIONING DATA
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