參數(shù)資料
型號(hào)： MT48V2M32LFFC
廠商： Micron Technology, Inc.
英文描述： 512K x 32 x 4 banks 2.5V SDRAM(2.5V,512K x 32 x 4組同步動(dòng)態(tài)RAM)
中文描述： 為512k × 32 × 4銀行2.5V的內(nèi)存電壓（2.5V，512K采樣× 32 × 4組同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 19/50頁(yè)
文件大?。?/td> 1058K
代理商： MT48V2M32LFFC
19
64Mb: x32 SDRAM, 2.5V
BatRam_25V.p65 – Rev. 0.7, Pub. 2/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
64Mb: x32, 2.5V
SDRAM
PRELIMINARY
Figure 15
WRITE To WRITE
Figure 14
WRITE Burst
Figure 13
WRITE Command
CS#
WE#
CAS#
RAS#
CKE
CLK
COLUMN
DON’T CARE
HIGH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
ABANK
A0–A7
A10
BA0, 1
A8, A9
VALID ADDRESS
CLK
DQ
D
IN
n
T2
T1
T3
T0
COMMAND
ADDRESS
NOP
NOP
WRITE
D
IN
n
+ 1
NOP
BANK,
COL
n
NOTE:
Burst length = 2. DQM is LOW.
CLK
DQ
T2
T1
T0
COMMAND
ADDRESS
NOP
WRITE
WRITE
BANK,
COL
n
BANK,
COL
b
D
IN
n
D
IN
n
+ 1
D
IN
b
NOTE:
DQM is LOW.
Each WRITE
command may be to any bank.
WRITEs
WRITE bursts are initiated with a WRITE command,
as shown in Figure 13.
The starting column and bank addresses are pro-
vided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric WRITE commands used in the following illustra-
tions, auto precharge is disabled.
During WRITE bursts, the first valid data-in ele-
ment will be registered coincident with the WRITE com-
mand. Subsequent data elements will be registered on
each successive positive clock edge. Upon completion
of a fixed-length burst, assuming no other commands
have been initiated, the DQs will remain High-Z and
any additional input data will be ignored (see Figure
14). A full-page burst will continue until terminated.
(At the end of the page, it will wrap to column 0 and
continue.)
Data for any WRITE burst may be truncated with a
subsequent WRITE command, and data for a fixed-
length WRITE burst may be immediately followed by
data for a WRITE command. The new WRITE command
can be issued on any clock following the previous WRITE
command, and the data provided coincident with the
new command applies to the new command. An ex-
ample is shown in Figure 15. Data
n
+ 1 is either the last
of a burst of two or the last desired of a longer burst.
This 64Mb SDRAM uses a pipelined architecture and
therefore does not require the 2
n
rule associated with a
prefetch architecture. A WRITE command can be initi-
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