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參數(shù)資料
| 型號： | MT48V2M32LFFC |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 512K x 32 x 4 banks 2.5V SDRAM(2.5V,512K x 32 x 4組同步動態(tài)RAM) |
| 中文描述： | 為512k × 32 × 4銀行2.5V的內(nèi)存電壓（2.5V，512K采樣× 32 × 4組同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 17/50頁 |
| 文件大?。?/td> | 1058K |
| 代理商： | MT48V2M32LFFC |
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17
64Mb: x32 SDRAM, 2.5V
BatRam_25V.p65 – Rev. 0.7, Pub. 2/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
64Mb: x32, 2.5V
SDRAM
PRELIMINARY
A fixed-length READ burst may be followed by, or
truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not acti-
vated), and a full-page burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued
x
cycles be-
fore the clock edge at which the last desired data ele-
ment is valid, where
x
equals the CAS latency minus
one. This is shown in Figure 11 for each possible CAS
latency; data element
n
+ 3 is either the last of a burst of
four or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to
the same bank cannot be issued until
t
RP is met. Note
that part of the row precharge time is hidden during
the access of the last data element(s).
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
NOP
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
PRECHARGE
ACTIVE
tRP
T7
NOTE:
DQM is LOW.
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
NOP
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
PRECHARGE
ACTIVE
tRP
T7
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
BANK
a
,
COL
n
NOP
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
PRECHARGE
ACTIVE
tRP
T7
BANK
a
,
ROW
BANK
(
a
or all)
DON’T CARE
X
= 0 cycles
CAS Latency = 1
X
= 1 cycle
CAS Latency = 2
CAS Latency = 3
BANK
a
,
COL
n
BANK
a
,
ROW
BANK
(
a
or all)
BANK
a
,
COL
n
BANK
a
,
ROW
BANK
(
a
or all)
X
= 2 cycles
Figure 11
READ To PRECHARGE
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