參數(shù)資料
型號(hào): MT48H8M16LFB4-8IT:JTR
元件分類: DRAM
英文描述: 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54
封裝: 8 X 8 MM, LEAD FREE, VFBGA-54
文件頁數(shù): 16/61頁
文件大小: 2469K
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. A 6/06 EN
23
2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
READs
Preliminary
PRECHARGE command, a subsequent command to the same bank cannot be issued
until tRP is met. Note that part of the row precharge time is hidden during the access of
the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvan-
tage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length bursts.
Figure 12:
READ-To-WRITE
Notes:
1. The READ command may be to any bank, and the WRITE command may be to any bank. If a
burst of one is used, then DQM is not required.
Figure 13:
READ-To-WRITE with Extra Clock Cycle
Notes:
1. The READ command may be to any bank, and the WRITE command may be to any bank.
READ
NOP
WRITE
NOP
CLK
T2
T1
T4
T3
T0
DQM
DQ
DOUT n
COMMAND
DIN b
ADDRESS
BANK,
COL n
BANK,
COL b
DS
tHZ
t
tCK
DON’T CARE
CL = 3
DON’T CARE
READ
NOP
DQM
CLK
DQ
DOUT n
T2
T1
T4
T3
T0
COMMAND
ADDRESS
BANK,
COL n
WRITE
DIN b
BANK,
COL b
T5
DS
tHZ
t
TRANSITIONING DATA
CL = 3
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT48H8M16LFF3-7E 制造商:Micron Technology Inc 功能描述:
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