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參數(shù)資料
| 型號(hào)： | MT48H8M16LFB4-8IT:JTR |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| 封裝： | 8 X 8 MM, LEAD FREE, VFBGA-54 |
| 文件頁數(shù)： | 15/61頁 |
| 文件大?。?/td> | 2469K |
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PDF: 09005aef8237e877/Source: 09005aef8237e8d8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. A 6/06 EN
22
2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
READs
Preliminary
Figure 11:
Random READ Accesses
Notes:
1. Each READ command may be to any bank. DQM is LOW.
The DQM input is used to avoid I/O contention, as shown in Figure 12 and Figure 13 on
page 23. The DQM signal must be asserted (HIGH) at least 2 clocks prior to the WRITE
command (DQM latency is 2 clocks for output buffers) to suppress data-out from the
READ. Once the WRITE command is registered, the DQ will go High-Z (or remain High-
Z), regardless of the state of the DQM signal, provided the DQM was active on the clock
just prior to the WRITE command that truncated the READ command. If not, the second
WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in Figure 14
on page 24, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would
be invalid.
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 13 on
page 23 shows the case where the clock frequency allows for bus contention to be
avoided without adding a NOP cycle, and Figure 13 on page 23 shows the case where the
additional NOP is needed. A fixed-length READ burst may be followed by, or truncated
with, a PRECHARGE command to the same bank (provided that auto precharge was not
activated). The PRECHARGE command should be issued x cycles before the clock edge
at which the last desired data element is valid, where x equals the CAS latency minus
one. This is shown in Figure 14 on page 24 for each possible CAS latency; data element n
+ 3 is either the last of a burst of four or the last desired of a longer burst. Following the
CLK
DQ
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
DON’T CARE
DOUT
n
DOUT
a
DOUT
x
DOUT
m
READ
NOP
BANK,
COL a
BANK,
COL x
BANK,
COL m
CLK
DQ
DOUT
n
T2
T1
T4
T3
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
DOUT
a
DOUT
x
DOUT
m
READ
NOP
BANK,
COL a
BANK,
COL x
BANK,
COL m
CL = 2
CL = 3
TRANSITIONING DATA
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| MT48H8M16LFF3-7E | 制造商:Micron Technology Inc 功能描述: |
| MT48H8M16LFF4-10 | 功能描述:IC SDRAM 128MBIT 100MHZ 54VFBGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869 |
| MT48H8M16LFF4-10 IT | 功能描述:IC SDRAM 128MBIT 100MHZ 54VFBGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869 |
| MT48H8M16LFF4-8 | 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869 |
| MT48H8M16LFF4-8 IT | 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869 |
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