參數(shù)資料
型號： MT48H8M16LFB4-8IT:JTR
元件分類： DRAM
英文描述： 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54
封裝： 8 X 8 MM, LEAD FREE, VFBGA-54
文件頁數(shù)： 13/61頁
文件大?。?/td> 2469K
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. A 6/06 EN
20
2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
READs
Preliminary
Data from any READ burst may be truncated with a subsequent READ command, and
data from a fixed-length READ burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst follows either the last element of a completed burst or the
last desired data element of a longer burst that is being truncated. The new READ
command should be issued x cycles before the clock edge at which the last desired data
element is valid, where x equals the CAS latency minus one.
This is shown in Figure 10, "Consecutive READ Bursts," on page 21 for CAS latencies of
two and three; data element n + 3 is either the last of a burst of four or the last desired of
a longer burst. The 128Mb SDRAM uses a pipelined architecture and therefore does not
require the 2n rule associated with a prefetch architecture. A READ command can be
initiated on any clock cycle following a previous READ command. Full-speed random
read accesses can be performed to the same bank, as shown in Figure 11, "Random
READ Accesses," on page 22, or each subsequent READ may be performed to a different
bank.
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQ go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
Figure 9:
READ Command
CS#
WE#
CAS#
RAS#
CKE
CLK
COLUMN
ADDRESS
A10
BA0,1
DON’T CARE
HIGH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
ADDRESS
A0-A8
A9, A11
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT48H8M16LFF3-7E 制造商:Micron Technology Inc 功能描述:
MT48H8M16LFF4-10 功能描述:IC SDRAM 128MBIT 100MHZ 54VFBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1 系列:- 格式 - 存儲器:RAM 存儲器類型:SDRAM 存儲容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869
MT48H8M16LFF4-10 IT 功能描述:IC SDRAM 128MBIT 100MHZ 54VFBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1 系列:- 格式 - 存儲器:RAM 存儲器類型:SDRAM 存儲容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869
MT48H8M16LFF4-8 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1 系列:- 格式 - 存儲器:RAM 存儲器類型:SDRAM 存儲容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869
MT48H8M16LFF4-8 IT 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1 系列:- 格式 - 存儲器:RAM 存儲器類型:SDRAM 存儲容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869
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