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參數(shù)資料
| 型號： | MSM548333 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 240,384-Word×8-bit + 240,384-Word×4-bit Triple Port type Field Memory(雙存儲塊分別為240,384字×8位和240,384字×4位三口型場存儲器) |
| 中文描述： | 240384 -字× 8位240384 -字× 4位的三場端口類型內(nèi)存（雙存儲塊分別為240384字× 8位和240384字× 4位三口型場存儲器） |
| 文件頁數(shù)： | 9/42頁 |
| 文件大?。?/td> | 421K |
| 代理商： | MSM548333 |
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Semiconductor
MSM548333
9/42
WRITE RELATED
WCLK : Write Clock for Y and C
WCLK is a write control clock input for Y and C ports. Synchronized with WCLK's rising edge, serial
write access into Y and C ports is executed when WE/WY is high and IE is high. (Note that the read
port is dual port, Y1 and C1 + Y2 and C2, but write port has only one port, Y + C. X8 of Y and X4 of
C inputs are controlled by a common WCLK, that is, in the write port, the MSM548333 is controlled
as a X12 FRAM.)
According to WCLK clocks, the internal counter for the serial address is incremented automatically.
In a write address set cycle, all the write addresses which were input from WXAD and WYAD are
stored into internal address registers synchronously with WCLK. In this address set cycle, WADE/
RX must be held high and WR/TR must be held low.
In the write address reset cycle, various write address reset modes can be set synchronously with
WCLK. These reset cycles replace complicated serial address control with simple reset cycle control
which requires only one WCLK cycle. It greatly facilitates memory access.
WE/WY : Write Enable for Y and C/Write Y Address Reset Logic Function
WE/WY is a dual function control input. WE, one of the two functions of WE/WY, is write enable.
WE enables or disables both internal write address pointers and data-in buffers of Y and C. When
WE/WY is high, the internal write address pointer for Y and C is incremented synchronously with
WCLK. When WE/WY is low, even if WCLK is input, the internal write address pointer is not
incremented.
WY, the second function of WE/WY, performs a function for setting the write Y address (or bit
address in a certain line) reset mode in Y and C. In a write address reset mode cycle, defined by WR/
TR high, WY works as one of inputs which form several write reset logic as shown in the "FUNCTION
TABLE for write". In the address reset cycle, when WE/WY level is low, each Y and C internal write
Y address is reset to 0. When WE/WY is high, each Y and C internal write Y address is reset to the
respective address which was set in the previous write address set cycle.
DINY/0-7 : Data-Ins for Y
DINY/0-7 are serial data-ins for Y. Each corresponding data-in-buffer is masked by IE.
DINC/0-3 : Data-Ins for C
DINC/0-3 are serial data-ins for C. Each corresponding data-in-buffer is masked by IE.
WR/TR : Write Reset for Y and C
WR/TR is a write reset control input for Y and C. Write address reset modes are defined when WR/
TR level is high according to the "FUNCTION TABLE for write".
WXINC : Write X Address Increment for Y and C
WXINC is a write X address (or line address) increment control input for Y and C. In the write address
reset cycle, defined by WR/TR high, the common write X address (or line address) for Y and C is
incremented by WXINC.
WADE/RX : Write Address Enable for Y and C/Write X Address Reset Logic Function
WADE/RX is a dual functional control input. WADE, one of the two functions of WADE/RX, is a
write address enable input for Y and C. In the write address reset cycle, defined by WR/TR high, X
address (or line address) and Y address (or bit address in a certain line) input from WXAD and
WYAD are latched into internal write X address register and Y address register.
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