
Semiconductor
MSM548333
7/42
RADE1/RX : Read Address Enable for Y1 and C1/Read X Address Reset Logic Function
RADE1/RX is a dual function control input. RADE1, one of the two functions of RADE1/RX, is a read
address enable input for Y1 and C1. In the read address set cycle, defined by RR1/TR low, X address
(or line address) and Y address (or bit address in a certain line) input from the RXAD1 pin and RYAD1
pin are latched into internal read X address register and Y address register, respectively synchronously
with RCLK.
RX, the second function of RADE1/RX, works as an element to set read X address (or line address)
reset mode. In an address reset mode cycle, defined by RR1/TR level high, RX works as one of inputs
which form several read reset logic as shown in the "FUNCTION TABLE for read".
RXAD1 : Read X Address for Y1 and C1
RXAD1 is a read X address (or line address) input for Y1 and C1. RXAD1 specifies the line address.
9 bits of read X address data are input serially from RXAD1.
RYAD1 : Read Y Address for Y1 and C1
RYAD1 is a read Y address (or bit address in a certain line) input for Y1 and C1. RYAD1 specifies the
first bit address of consecutive serial read data in the line whose line address is defined by the X read
address from RXAD1. 10 bits of Y address data are input serially from RYAD1.
RR2/TR : Read Reset for Y2 and C2
RR2/TR is a read reset control input for Y2 and C2. Read address reset modes for Y2 and C2 are
defined when RR2/TR level is high based on the "FUNCTION TABLE for read".
RXINC2 : Read X Address Increment for Y2 and C2
RXINC2 is a read X address (or line address) increment control input for Y2 and C2. In the read
address reset cycle, defined by RR2/TR high, the common read X address (or line address) for Y2
and C2 is incremented by RXINC2.
RADE2/RX : Read Address Enable for Y2 and C2/Read X Address Reset Logic Function
RADE2/RX is a dual function control input. RADE2, one of the two functions of RADE2/RX, is a read
address enable input for Y2 and C2. In the read address set cycle, defined by RR2/TR high, the read
X address (or line address) and the read Y address (or bit address in a certain line), which are input
from the RXAD2, RYADY2 and RYADC2 pins, are latched into internal read X address register and
read Y address register, respectively, synchronously with RCLK.
RX, the second function of RADE2/RX, performs a function for setting the read X address (or line
address) reset mode. In a read address reset mode cycle, defined by RR2/TR level high, RX works
as one of inputs which form several read reset logic as shown in the "FUNCTION TABLE for read".
RXAD2 : Read X Address for Y2 and C2
RXAD2 is a read X address (or line address) input for Y2 and C2. RXAD2 specifies the line address.
9 bits of X address data is input serially from RXAD2.
RYADY2 : Read Y Address for Y2
RYADY2 is a read Y address (or bit address in a certain line) input for Y2. RYADY2 specifies the first
bit address of serial read data in the line whose line address is specified by the X address RXAD2.
10 bits of Y address data are input serially from RYADY2.