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參數(shù)資料
| 型號： | MSM548333 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 240,384-Word×8-bit + 240,384-Word×4-bit Triple Port type Field Memory(雙存儲塊分別為240,384字×8位和240,384字×4位三口型場存儲器) |
| 中文描述： | 240384 -字× 8位240384 -字× 4位的三場端口類型內(nèi)存（雙存儲塊分別為240384字× 8位和240384字× 4位三口型場存儲器） |
| 文件頁數(shù)： | 6/42頁 |
| 文件大小： | 421K |
| 代理商： | MSM548333 |
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Semiconductor
MSM548333
6/42
PIN FUNCTION
(Note : Y1 = "port-1 of Y area", Y2 = "port-2 of Y area", C1 = "port-1 of C area",
C2 = "port-2 of C area "
READ RELATED
RCLK : Read Clock for Y1 and C1, Common Read Address Strobe Clock
RCLK is the read control clock input for Y1 and C 1. Synchronized with RCLK's rising edge, serial
read access from Y1 and C1 is executed when RE1/RY is high. (Note that the write port has one port,
Y and C, but the read port has dual ports, Y1 and C1 plus Y2 and C2. Y1 and C1 are controlled by the
common read clock RCLK. But Y2 and C2 are controlled by separated read clocks, RCLKY2 and
RCLKC2, asynchronously.)
The internal counter for the serial read address is incremented automatically on the rising edge of
RCLK. In a read address set cycle, all the read address bits which were input from each RXAD1, RYAD1,
RXAD2, RYADY2, and RYADC2 pins are stored into internal address registers synchronized
with RCLK. In this address set cycle, RADE1/RX and RADE2/RX must be held high and the RR1/
TR and RR2/TR must be held low.
In the read address reset cycle, various read address reset modes can be set synchronously with
RCLK. These reset cycles work to replace complicated serial address control which requires many
RCLK clocks with a simple reset cycle control requiring only a single RCLK cycle. It greatly facilitates
memory access.
RE1/RY : Read Enable for Y1 and C1/Read Y Address Reset Logic Function
RE1/RY is a dual function control input. RE1, one of the two functions of RE1/RY, is read enable.
RE1 enables or disables both internal read address pointers and data-out buffers of Y1 and C1. When
RE1/RY is high, the internal read address pointer for Y1 and C1 is incremented synchronously with
RCLK. When RE1/RY is low, even if the RCLK is input, the internal read address pointer is not
incremented.
RY, the second function of RE1/RY, performs a function for setting the read Y address (or bit address
in a certain line) reset mode in Y1 and C1. In a read address reset mode cycle, as defined by RR1/TR
being high, RY works as one of inputs which form several read reset logic as shown in the
"FUNCTION TABLE for read". In the address reset cycle, when RE1/RY level is low, each Y1and C1
internal read Y address is reset to 0. When RE1/RY is high, each Y1 and C1 internal read Y address
is reset to the respective address which was set in the previous read address set cycle.
DOY1/0-7 : Data-Outs for Y1
DOY1/0-7 are serial data-outs for Y1. Each corresponding data out buffer' impedance is controlled
by RE1/RY.
DOC1/0-3 : Data-Outs for C1
DOC1/0-3 are serial data-outs for C1. Each corresponding data out buffer' impedance is controlled
by RE1/RY.
RR1/TR : Read Reset for Y1 and C1
RR1/TR is a read reset control input for Y1 and C1. Read address reset modes are defined when RR1/
TR level is high according to the "FUNCTION TABLE for read".
RXINC1 : Read X Address Increment for Y1 and C1
RXINC1 is a read X address (or line address) increment control input for Y1 and C1. In the read
address reset cycle, defined by RR1/TR high, the common X address (or line address) for Y1 and C1
is incremented by RXINC1.
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