參數(shù)資料
型號(hào)： MSM548333
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： 240,384-Word×8-bit + 240,384-Word×4-bit Triple Port type Field Memory(雙存儲(chǔ)塊分別為240,384字×8位和240,384字×4位三口型場(chǎng)存儲(chǔ)器)
中文描述： 240384 -字× 8位240384 -字× 4位的三場(chǎng)端口類型內(nèi)存（雙存儲(chǔ)塊分別為240384字× 8位和240384字× 4位三口型場(chǎng)存儲(chǔ)器）
文件頁(yè)數(shù)： 11/42頁(yè)
文件大小： 421K
代理商： MSM548333
Semiconductor
MSM548333
11/42
OPERATION MODE
Write
1. Write operation
Before the write operation begins, X address (or line address) and Y address (or bit address
in the line specified by the X address) must be input to set the initial bit address for the
following serial write access. When WE/WY and IE are high, a set of serial 12-bit -width write
data on DINY/0-7 and DINC/0-3 is written into write registers attached to the DRAM
memory arrays temporarily on the rising edge of WCLK.
Following 12-bit-width serial input data is written into the memory locations in the write
register designated by an internal write address pointer which is advanced by WCLK. This
enables continuous serial write on a line. When write clock WCLK and read clock RCLK are
tied together and are controlled by a common clock or CLK, more than two MSM548333s can
be cascaded directly without any delay devices between the MSM548333s because the read
timing is delayed by one CLK cycle to the write timing. When the write operation on a line is
terminated, be sure to perform a write transfer operation by WR/TR in order to store the
written data in the write registers to the corresponding memory cells in the DRAM memory
arrays.
2. Write address pointer increment operation
The write address pointer is incremented synchronously with WCLK when WE/WY is high.
When the write address pointer reaches the last address of a line, it stops at the last address
and no address increment occurs.
Relationship between the WE/WY and IE input levels,
Write Address pointer, and data input status
When WE/WY and IE are high, the write operation is enabled.
If IE level goes low while WCLK is active, the write operation is halted but the write address
pointer will continue to advance. That is, IE enables a write mask function. When WE/WY
goes low, the write address pointer stops without WCLK.
Read
(Here, "port-1 of Y area" is Y1, "port-2 of Y area" is Y2, "port-1 of C area" is C1, "port-2 of C area"
is C2.)
1. Read operation
MSM548333 has dual read ports, port-1 for Y and C memory areas and port-2 for Y and C
memory areas. Note that the read of Y1 and C1 are controlled by a common control clock at
the same time. But the read of Y2 and C2 are controlled by separate sets of control clocks,
independently.
Before the read operation begins, the X address (or line address) and Y address (or bit address
in the line specified by the X address) must be input for setting initial bit address for the
following serial read access.
When RE1/RY is high, a set of serial 12-bit-width read data on DOY1/0-7 pins and DOC1/
0-3 pins is read from read registers attached to DRAM memory arrays on the rising edge of
RCLK.
When REY2/RY is high, a set of serial 8-bit-width read data on DOY2/0-7 pins is read from
read registers attached to DRAM memory arrays on the rising edge of RCLKY2.
WE/WY
H
H
L
IE
H
L
—
WCLK Rise
Internal Write
Address Pointer
Data Input
Incremented
Inputted
Not Inputted
Stopped
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