
MPC509
USER’S MANUAL
CENTRAL PROCESSING UNIT
Rev. 15 June 98
MOTOROLA
3-7
to deliver results in hardware that are adequate for most applications, if not in strict
conformance with IEEE standards. In this mode, denormalized numbers, NaNs, and
IEEE invalid operations are treated as legitimate, returning default results rather than
causing floating-point assist exceptions.
3.5 Levels of the PowerPC Architecture
The PowerPC architecture consists of three layers. Adherence to the PowerPC archi-
tecture can be measured in terms of which of the following levels of the architecture
are implemented:
PowerPC user instruction set architecture (UISA) — Defines the base user-level
instruction set, user-level registers, data types, floating-point exception model,
memory models for a uniprocessor environment, and programming model for a
uniprocessor environment.
PowerPC virtual environment architecture (VEA) — Describes the memory model
for a multiprocessor environment, defines cache control instructions, and de-
scribes other aspects of virtual environments. Implementations that conform to
the VEA also adhere to the UISA, but may not necessarily adhere to the OEA.
PowerPC operating environment architecture (OEA) — Defines the memory man-
agement model, supervisor-level registers, synchronization requirements, and
the exception model. Implementations that conform to the OEA also adhere to the
UISA and the VEA.
3.6 RCPU Programming Model
The PowerPC architecture defines register-to-register operations for most computa-
tional instructions. Source operands for these instructions are accessed from the
registers or are provided as immediate values embedded in the instruction opcode.
The three-register instruction format allows specification of a target register distinct
from the two source operands. Load and store instructions transfer data between
memory and on-chip registers.
PowerPC processors have two levels of privilege: supervisor mode of operation (typi-
cally used by the operating environment) and user mode of operation (used by the
application software). The programming models incorporate 32 GPRs, 32 FPRs, spe-
cial-purpose registers (SPRs), and several miscellaneous registers.
Supervisor-level access is provided through the processor’s exception mechanism.
That is, when an exception is taken (either due to an error or problem that needs to be
serviced, or deliberately through the use of a trap instruction), the processor begins
operating in supervisor mode. The level of access is indicated by the privilege-level
(PR) bit in the machine state register (MSR).
Figure 3-3
shows the user-level and supervisor-level RCPU programming models and
also illustrates the three levels of the PowerPC architecture. The numbers to the left
of the SPRs indicate the decimal number that is used in the syntax of the instruction
operands to access the register.