
MOTOROLA
5-30
SYSTEM INTERFACE UNIT
Rev. 15 June 98
MPC509
USER’S MANUAL
5.4.13 Show Cycles
Internal bus cycles that are echoed on the external bus are referred to as show cycles.
By providing access to bus cycles that are not visible externally during normal opera-
tion, show cycles allow a development support system to trace the flow of a program.
The LSHOW field in the SIUMCR can be programmed to cause the EBI to echo certain
or all internal L-bus cycles on the external bus. Likewise, the ISCTL field in the ICTRL
register (instruction bus control register, SPR 158) in the RCPU can be programmed
to cause the EBI to echo certain or all internal I-bus cycles on the external bus.
0011
PRU select (not supported in
MPC509)
This is a normal external bus cycle access to a port replacement chip
used for emulation support. Both the address and the data phase are
seen on the external bus. This cycle requires an AACK and a TA signal.
It indicates that an access was made which would have gone to an in-
ternal port control register if the chip were not operating in PRU mode.
These are internal visibility cycles. This cycle is self-terminating and
does not require AACK and TA signals. These encodings indicate that
an access or aborted fetch (resulting from either a cache hit or a specu-
lative load that is subsequently discarded) was made to an address on
the internal I-bus or L-bus. An instruction access (AT1 = 1) with an ad-
dress which is an indirect branch target is indicated as a write on the WR
signal.
0100
I-mem (not supported in
MPC509)
The I-Mem cycle type is not supported in the MPC509.
This is an internal visibility cycle. It always has an address phase and
includes a data phase for data accesses. This cycle is self-terminating
and does not require AACK and TA signals. It indicates that an access
was made to an address on the external bus and that a cache hit or
aborted fetch occurred. An instruction access with an address that is an
indirect branch target is indicated as a write on the WR signal.
This is an internal visibility cycle. It always has an address phase and a
data phase. This cycle is self-terminating and does not require AACK
and TA signals. It indicates that an access was made to a control regis-
ter or internal IMB2 address. These accesses are always cache-inhibit-
ed.
0101
L-mem
0110
E-Mem (external memory)
cache hit, not using a chip se-
lect
0111
Internal register
1000
E-Mem cache hit
to CSBOOT region
E-Mem cache
hit to CS1 region
E-Mem cache
hit to CS2 region
E-Mem cache
hit to CS3 region
E-Mem cache
hit to CS4 region
E-Mem cache
hit to CS5 region
Reserved
Reserved
These are internal visibility cycles. They always have an address phase
and include a data phase for data accesses. These cycles are self-ter-
minating and do not require AACK and TA signals. These encodings in-
dicate that an access was made to an address on the external bus and
that a cache hit or aborted fetch occurred. An instruction access with an
address that is an indirect branch target is indicated as a write on the
WR signal.
The region indicated is the main chip-select region, not the sub-region.
1001
1010
1011
1100
1101
1110
1111
—
—
Table 5-14 Cycle Type Encodings (Continued)
CT[0:3]
Cycle Type
Description