Figure
Title
Page
LIST OF FIGURES
MPC509
USER’S MANUAL
LIST OF FIGURES
Rev. 15 June 1998
MOTOROLA
xiii
1-1
1-2
1-3
1-4
MPC509 Block Diagram ................................................................................. 1-2
MPC509 Pin Assignments .............................................................................. 1-3
MPC509 Signals ............................................................................................. 1-4
MPC509 Memory Map .................................................................................... 1-5
2-1
Output-Only and Three-State I/O Buffers ....................................................... 2-2
3-1
3-2
3-3
3-4
RCPU Block Diagram ..................................................................................... 3-2
Sequencer Data Path ..................................................................................... 3-4
RCPU Programming Model ............................................................................ 3-9
Basic Instruction Pipeline ............................................................................. 3-34
4-1
4-2
Instruction Cache Organization ...................................................................... 4-2
Instruction Cache Data Path ........................................................................... 4-3
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25
5-26
SIU Block Diagram ......................................................................................... 5-2
Internal Module Select Scheme ...................................................................... 5-8
Placement of Internal Memory in Memory Map .............................................. 5-9
Flow Diagram of a Single Read Cycle .......................................................... 5-16
Example of a Read Cycle ............................................................................. 5-17
Flow Diagram of a Single Write Cycle .......................................................... 5-18
Example of Pipelined Bus ............................................................................. 5-19
Write Followed by Two Reads on the E-Bus (Using Chip Selects) .............. 5-19
External Burst Read Cycle ........................................................................... 5-23
Storage Reservation Signaling ..................................................................... 5-32
Simplified Uniprocessor System with Chip-Select Logic .............................. 5-34
Chip-Select Functional Block Diagram ......................................................... 5-36
Multi-Level Protection ................................................................................... 5-46
Chip-Select Operation Flowchart .................................................................. 5-56
Overlapped Accesses to the Same Region .................................................. 5-57
Pipelined Accesses to Two Different Regions .............................................. 5-58
Asynchronous Read (Zero Wait States) ....................................................... 5-60
Asynchronous Write (Zero Wait States) ....................................................... 5-60
Synchronous Read with Asynchronous OE (Zero Wait States) ................... 5-61
Synchronous Write (Zero Wait States) ......................................................... 5-61
Synchronous Read with Early OE (One Wait State) .................................... 5-62
Synchronous Read with Early Overlap (One Wait State) ............................. 5-63
Type 1 Synchronous Burst Read Interface ................................................... 5-64
Type 1 Synchronous Burst Write Interface ................................................... 5-65
Type 2 Synchronous Burst Read Interface ................................................... 5-66
SIU Clock Module Block Diagram ................................................................ 5-69