參數資料
型號: MPC5200ID
廠商: Motorola, Inc.
英文描述: MPC5200 Hardware Specifications
中文描述: MPC5200的硬件規(guī)格
文件頁數: 1/76頁
文件大?。?/td> 1404K
代理商: MPC5200ID
NOTE:
The information in this document is subject to
change. For the latest data on the MPC5200, visit
www.mobilegt.com and proceed to the MPC5200
Product Summary Page.
1
Overview
The MPC5200 integrates a high performance MPC603e series G2_LE core with a
rich set of peripheral functions focused on communications and systems
integration. The G2_LE core design is based on the PowerPC
core architecture.
MPC5200 incorporates an innovative BestComm I/O subsystem, which isolates
routine maintenance of peripheral functions from the embedded G2_LE core. The
MPC5200 contains a SDRAM/DDR Memory Controller, a flexible External Bus
Interface, PCI Controller, USB, ATA, Ethernet, six Programmable Serial Controllers
(PSC), I
2
C, SPI, CAN, J1850, Timers, and GPIOs.
2
Features
Key features are shown below.
MPC603e series G2_LE core
— Superscalar architecture
— 760 MIPS at 400 MHz (-40 to +85
o
C)
— 16 k Instruction cache, 16 k Data cache
— Double precision FPU
— Instruction and Data MMU
— Standard and Critical interrupt capability
SDRAM / DDR Memory Interface
— up to 132-MHz operation
— SDRAM and DDR SDRAM support
— 256-MByte addressing range per CS, two CS available
— 32-bit data bus
— Built-in initialization and refresh
Flexible multi-function External Bus Interface
— Supports interfacing to ROM/Flash/SRAM memories or other memory
mapped devices
MPC5200/D
Rev. 2, 5/2004
MPC5200 Hardware
Specifications
Topic
1
2
3
Page
Overview ......................................1
Features .......................................1
Electrical and Thermal
Characteristics..............................5
Package Description ..................60
System Design Information ........69
Ordering Information ..................74
Document Revision History........75
4
5
6
7
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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