參數(shù)資料
型號(hào)： MPC5200ID
廠商： Motorola, Inc.
英文描述： MPC5200 Hardware Specifications
中文描述： MPC5200的硬件規(guī)格
文件頁(yè)數(shù)： 14/76頁(yè)
文件大?。?/td> 1404K
代理商： MPC5200ID
14
MPC5200 Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
3.2.4 G2_LE Core PLL Electrical Characteristics
The internal clocking of the G2_LE core is generated from and synchronized to the system clock by means
of a voltage-controlled core PLL.
Table 11 G2_LE PLL Specifications
Characteristic
Symbol
Notes
Min
Typical
Max
Unit
SpecID
G2_LE frequency
f
core
1
1
The SYSCLK frequency and G2_LE PLL Configuration bits must be chosen such that the resulting system frequencies,
CPU (core) frequency, and G2_LE PLL (VCO) frequency do not exceed their respective maximum or minimum oper-
ating frequencies.
This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different types
of jitter can exist on the input to core_sysclk, systemic and true random jitter. True random jitter is rejected, but the PLL.
Systemic jitter will be passed into and through the PLL to the internal clock circuitry, directly reducing the operating fre-
quency.
Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for
the PLL lock after a stable Vdd and core_sysclk are reached during the power-on reset sequence. This specification
also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
50
—
550
MHz
O4.1
G2_LE cycle time
t
core
1
2.85
—
40.0
ns
O4.2
G2_LE VCO frequency
f
VCOcore
1
400
—
1200
MHz
O4.3
G2_LE input clock frequency
f
SYSCLK
25
—
367
MHz
O4.4
G2_LE input clock cycle time
t
SYSCLK
2.73
—
50.0
ns
O4.5
G2_LE input clock jitter
t
jitter
2
2
—
—
150
ps
O4.6
G2_LE PLL relock time
t
lock
3
3
—
—
100
μ
s
O4.7
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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