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參數(shù)資料
| 型號： | MPC5200ID |
| 廠商： | Motorola, Inc. |
| 英文描述： | MPC5200 Hardware Specifications |
| 中文描述： | MPC5200的硬件規(guī)格 |
| 文件頁數(shù)： | 8/76頁 |
| 文件大?。?/td> | 1404K |
| 代理商： | MPC5200ID |
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8
MPC5200 Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
3.1.4 Electrostatic Discharge
— CAUTION —
This device contains circuitry that protects against damage due to high-static voltage
or electrical fields. However, it is advised that normal precautions be taken to avoid
application of any voltages higher than maximum-rated voltages. Operational reliability
is enhanced if unused inputs are tied to an appropriate logic voltage level (i.e., either
GND or V
CC
).
Table 7
gives package thermal characteristics for this device.
3.1.5 Power Dissipation
Power dissipation of the MPC5200 is caused by 3 different components: the dissipation of the internal or
core digital logic (supplied by VDD_CORE), the dissipation of the analog circuitry (supplied by
SYS_PLL_AVDD and CORE_PLL_AVDD) and the dissipation of the IO logic (supplied by VDD_IO_MEM
and VDD_IO).
Table 6
details typical measured core and analog power dissipation figures for a range of
operating modes. However, the dissipation due to the switching of the IO pins can not be given in general,
but must be calculated by the user for each application case using the following formula
where N is the number of output pins switching in a group M, C is the capacitance per pin, VDD_IO is the
IO voltage swing, f is the switching frequency and PIOint is the power consumed by the unloaded IO stage.
The total power consumption of the MPC5200 processor
must not exceed the value, which would cause the maximum junction temperature to be exceeded.
Table 5 ESD and Latch-Up Protection Characteristics
Sym
Rating
Min
Max
Unit
SpecID
V
HBM
Human Body Model (HBM)—JEDEC JESD22-A114-B
2000
—
V
D4.1
V
MM
Machine Model (MM)—JEDEC JESD22-A115
200
—
V
D4.2
V
CDM
Charge Device Model (CDM)—JEDEC JESD22-C101
500
—
V
D4.3
I
LAT
Latch-up Current at T
A
=85
o
C
positive
negative
+100
-100
—
mA
D4.4
I
LAT
Latch-up Current at T
A
=27
o
C
positive
negative
+200
-200
—
mA
D4.5
P
IO
P
IOint
N
M
∑
+
C
VDD_IO
2
f
×
×
×
=
P
total
P
core
P
analog
P
IO
+
+
=
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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