參數(shù)資料
型號(hào)： MPC5200ID
廠商： Motorola, Inc.
英文描述： MPC5200 Hardware Specifications
中文描述： MPC5200的硬件規(guī)格
文件頁(yè)數(shù)： 69/76頁(yè)
文件大小： 1404K
代理商： MPC5200ID
MOTOROLA
MPC5200 Hardware Specifications
69
System Design Information
6
System Design Information
6.1
Figure 50
shows situations in sequencing the I/O VDD (VDD_IO), Memory VDD (VDD_IO_MEM), PLL
VDD (PLL_AVDD), and Core VDD (VDD_CORE).
Power UP/Down Sequencing
Figure 50 Supply Voltage Sequencing
The relationship between VDD_IO_MEM and VDD_IO is non-critical during power-up and power-down
sequences. Both VDD_IO_MEM (2.5 V or 3.3 V) and VDD_IO are specified relative to VDD_CORE.
6.1.1 Power Up Sequence
If VDD_IO/VDD_IO_MEM are powered up with the VDD_CORE at 0V, the sense circuits in the I/O pads
will cause all pad output drivers connected to the VDD_IO/VDD_IO_MEM to be in a high-impedance state.
There is no limit to how long after VDD_IO/VDD_IO_MEM powers up before VDD_CORE must power up.
VDD_CORE should not lead the VDD_IO, VDD_IO_MEM or PLL_AVDD by more than 0.4 V during power
ramp up or there will be high current in the internal ESD protection diodes. The rise times on the power
supplies should be slower than 1 microsecond to avoid turning on the internal ESD protection clamp
diodes.
The recommended power up sequence is as follows:
Use one microsecond or slower rise time for all supplies.
1.5V
2.5V
3.3V
0
D
VDD_IO,
VDD_IO_MEM (SDR)
VDD_IO_MEM (DDR)
VDD_CORE,
PLL_AVDD
Note:
1.
VDD_CORE should not exceed VDD_IO, VDD_IO_MEM or PLL_AVDD by more than 0.4 V at any time,
including power-up.
It is recommended that VDD_CORE/PLL_AVDD should track VDD_IO/VDD_IO_MEM up to 0.9 V
then separate for completion of ramps.
Input voltage must not be greater than the supply voltage (VDD_IO, VDD_IO_MEM, VDD_CORE, or
PLL_AVDD) by more than 0.5 V at any time, including during power-up.
Use 1 microsecond or slower rise time for all supplies.
2.
3.
4.
1
2
Time
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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