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參數(shù)資料
| 型號： | MPC5200ID |
| 廠商： | Motorola, Inc. |
| 英文描述： | MPC5200 Hardware Specifications |
| 中文描述： | MPC5200的硬件規(guī)格 |
| 文件頁數(shù)： | 34/76頁 |
| 文件大小： | 1404K |
| 代理商： | MPC5200ID |
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34
MPC5200 Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
Figure 15 Timing Diagram—Initiating an Ultra DMA Data In Burst
(t)
ZIORDY
0
—
0
—
0
—
Minimum time drive waits before driving
IORDY
A8.44
(t)
ACK
20
—
20
—
20
—
Setup and hold times for DMACK, before
assertion or negation.
A8.45
(t)
SS
50
—
50
—
50
—
Time from STROBE edge to negation of
DMARQ or assertion of STOP, when sender
terminates a burst.
A8.46
1
t
UI
, t
MLI
, t
LI
indicate sender-to-recipient or recipient-to-sender interlocks. That is, one agent (either sender or recipient) is
waiting for the other agent to respond with a signal before proceeding.
t
UI
is an unlimited interlock that has no maximum time value.
t
MLI
is a limited time-out that has a defined minimum.
t
LI
is a limited time-out that has a defined maximum.
All timing parameters are measured at the connector of the drive to which the parameter applies. For example, the sender
shall stop generating STROBE edges t
RFS
after negation of DMARDY. Both STROBE and DMARDY timing measure-
ments are taken at the connector of the sender. Even though the sender stops generating STROBE edges, the receiver
may receive additional STROBE edges due to propagation delays. All timing measurement switching points (low to high
and high to low) are taken at 1
.
5 V.
2
Table 28 Ultra DMA Timing Specification (continued)
Name
MODE 0
(ns)
MODE 1
(ns)
MODE 2
(ns)
Comment
SpecID
Min
Max
Min
Max
Min
Max
t
UI
t
ACK
t
AZ
t
ACK
t
ACK
t
ZAD
t
FS
t
FS
t
ENV
t
ENV
t
ZIORDY
t
DVS
t
DVH
t
ZAD
DMARQ
(device)
DMACK
(device)
STOP
(host)
HDMARDY
(host)
DSTROBE
(device)
DD(0:15)
DA0, DA1, DA2,
CS[0:1]1
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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