參數(shù)資料
型號(hào): MPC5200ID
廠商: Motorola, Inc.
英文描述: MPC5200 Hardware Specifications
中文描述: MPC5200的硬件規(guī)格
文件頁(yè)數(shù): 41/76頁(yè)
文件大?。?/td> 1404K
代理商: MPC5200ID
MOTOROLA
MPC5200 Hardware Specifications
41
Electrical and Thermal Characteristics
Figure 27 Ethernet Timing Diagram—MII Tx Signal
Figure 28 Ethernet Timing Diagram—MII Async
1
the TX_CLK frequency shall be 25% of the nominal transmit frequency, e.g., a PHY operating at 100 Mb/s must provide
a TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5 MHz. See the
IEEE 802.3 Specification [6].
Table 32 MII Async Signal Timing
Sym
Description
Min
Max
Unit
SpecID
M8
CRS, COL minimum pulse width
1
.
5
TX_CLK Period
A9.8
Table 33 MII Serial Management Channel Signal Timing
Sym
Description
Min
Max
Unit
SpecID
M9
MDC falling edge to MDIO output delay
0
25
ns
A9.9
M10
MDIO (input) to MDC rising edge setup
10
ns
A9.10
M11
MDIO (input) to MDC rising edge hold
MDC pulse width high
1
MDC pulse width low
1
MDC period
2
10
ns
A9.11
M12
1
MDC is generated by MPC5200 with a duty cycle of 50% except when MII_SPEED in the FEC MII_SPEED control
register is changed during operation. See the MPC5200 User Manual [1].
160
ns
A9.12
M13
160
ns
A9.13
M14
400
ns
A9.14
M7
M6
M5
TX_CLK (Input)
TXD[3:0] (Outputs)
TX_EN
TX_ER
M8
CRS, COL
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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