Figure
Title
Page
MOTOROLA
xiv
LIST OF FIGURES
Rev. 15 June 1998
MPC509
USER’S MANUAL
5-27
5-28
5-29
5-30
5-31
5-32
Phase-Locked Loop Block Diagram ............................................................. 5-72
Crystal Oscillator .......................................................................................... 5-73
Charge Pump with Loop Filter Schematic .................................................... 5-73
Periodic Interrupt Timer Block Diagram ........................................................ 5-87
External Reset Request Flow ....................................................................... 5-94
Internal Reset Request Flow ........................................................................ 5-96
6-1
6-2
6-3
Peripherals Control Unit Block Diagram ......................................................... 6-1
Interrupt Structure Block Diagram .................................................................. 6-6
Time-Multiplexing Protocol For IRQ Pins ....................................................... 6-8
7-1
Placement of Internal SRAM in Memory Map ................................................ 7-2
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
Watchpoint and Breakpoint Support in the RCPU ........................................ 8-12
Partially Supported Watchpoint/Breakpoint Example ................................... 8-15
I-Bus Support General Structure .................................................................. 8-16
L-Bus Support General Structure ................................................................. 8-18
Development Port Support Logic .................................................................. 8-22
Development Port Registers and Data Paths ............................................... 8-24
Enabling Clock Mode Following Reset ......................................................... 8-27
Asynchronous Clocked Serial Communications ........................................... 8-28
Synchronous Clocked Serial Communications ............................................. 8-29
Synchronous Self-Clocked Serial Communications ..................................... 8-30
Enabling Debug Mode at Reset .................................................................... 8-35
Entering Debug Mode Following Reset ........................................................ 8-36
General Port Usage Sequence Diagram ...................................................... 8-40
Debug Mode Logic ....................................................................................... 8-44
9-1
9-2
9-3
9-4
9-5
9-6
JTAG Pins ...................................................................................................... 9-1
Test Logic Block Diagram ............................................................................... 9-2
Sample EXTEST Connection ......................................................................... 9-4
Bypass Register ............................................................................................. 9-5
Typical Clamp Example .................................................................................. 9-6
IDREGISTER Configuration ........................................................................... 9-7