MPC509
USER’S MANUAL
SYSTEM INTERFACE UNIT
Rev. 15 June 98
MOTOROLA
5-29
phase. That is, the EBI generates AACK and TA internally and generates an internal
error signal for that cycle. If AACK has already been asserted externally, the EBI gen-
erates TA but not AACK internally and generates an internal error signal for that cycle.
All transfer errors that occur during an access to a 16-bit port terminate the cycle cur-
rently in progress. If an error occurs during any part of a word access to a 16-bit port,
the current access is terminated. Subsequent bus cycles of the small port access will
continue, but TEA will be asserted internally with each beat.
All illegal accesses to internal registers are terminated with a data error, causing the
bus monitor to assert the internal TEA signal. Accesses to unimplemented internal
memory locations and privilege violations (user access to supervisor register or write
to read-only location or a write to register which is locked) also cause the bus monitor
to assert the internal TEA signal.
Note that the chip-select module can also assert the internal TEA signal. Refer to
5.5.7
Access Protection
for more information.
5.4.12 Cycle Types
The cycle type pins (CT[0:3]) are address-phase signals that provide information
about the type of internal or external bus cycle in progress. These pins can be used by
an external development system to construct a program trace.
Table 5-14
summarizes the cycle type encodings. Refer to the RCPU Reference Man-
ual(RCPURM/AD) for details on how a development system can use the information
provided by these pins.
Table 5-14 Cycle Type Encodings
CT[0:3]
Cycle Type
Description
0000
Normal bus cycle
This is a normal external bus cycle. Both the address and data phase
are seen on the external bus. This cycle requires an AACK and a TA sig-
nal. This cycle type is used for sequential fetches and for prefetches of
predicted branch targets where the branch condition has not been eval-
uated before the prefetch. It is also used for all non-reservation type
load/store cycles.
If the address type is data (AT1 = 0), then this is a data access to the
external bus. Both the address and the data phase are seen on the ex-
ternal bus. This cycle requires an AACK and a TA signal. When this cy-
cle starts, external snooping logic should latch the address to track the
reservation.
If the address type is instruction (AT1 = 1), then this is an instruction
fetch cycle marked as an indirect change-of-flow cycle. Both the address
and the data phase are seen on the external bus. This cycle requires an
AACK and a TA signal. This cycle type is used when an external ad-
dress is the destination of a branch instruction or the destination of an
exception or VSYNC cycle.
This is a special external bus cycle to emulation memory replacing inter-
nal I-mem or L-mem (and not resulting in a cache hit). The MPC509
does not support this cycle type.
0001
Reservation start if
address type is data
OR
Instruction fetch marked
as indirect change-of-flow if ad-
dress
type is instruction
0010
Emulation memory select (not
supported in MPC509)